Hall Ticket No Question Paper Code: AEC002
INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
B.Tech III Semester End Examinations (Regular) November, 2018
Regulation: IARE R16
DIGITAL SYSTEM DESIGN
Time: 3 Hours Max Marks: 70
Answer ONE Question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
UNIT I
1. Add the following binary numbers.
11011+1101
ii) 10111.101 110111.01
iii) 1010.11 1101.10
Convert the following numbers from the given base to the other bases indicated.
Decimal 225 to binary, octal
ii) Octal 623 to decimal, binary
2. The state of a 12-bit register is 010110010111. What is its content if it represents:
three decimal digits in BCD
ii) three decimal digits in Excess-3 code
Add the following BCD numbers
1001 and 0100
ii) 00010110 and 00010101
UNIT II
3. Demonstrate the validity of the following identities by means of truth tables.
i. DeMorgan's Theorem for three variables
ii. Associative Law
Simply the following boolean expressions to a minimum number of literals.
i. xyz xyz'
ii. xyz' x'yz xyz
4. Simplify the following Boolean function using, four-variable K-map
F B 10, 13,15)
Simplify the following using Quine-McClusky minimization technique.
Y F A0B0C0 A0B0C A0BC AB0C
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UNIT III
5. Design a combinational circuit with three inputs and z and three outputs B and C. When
the binary input is or the binary output is one greater than the input. When the
binary input is or the binary output is one less than the input.
Implement full subtractor using NAND gates.
6. Design a combinational circuit that adds 4-bit number. The circuit can be designed using four
full-adders.
Design a combinational circuit with four inputs that represent a decimal digit in BCD and four
outputs that produce the complement of the input digit.
UNIT IV
7. Explain the operation of MSJK flip-flop using NAND gates.
Draw the logic diagram of mod 6 ripple counter using T flip-flops.
8. Design a 3 bit binary Up-Down counter with necessary diagrams.
Design a bi-directional shift register with necessary diagrams.
UNIT V
9. Explain how the behavior of a clocked synchronous sequential circuit is described by a state table
and discuss the method of state table reduction.
Convert the following Moore machine into corresponding Mealy machine as per given in Table 1.

Table 1
Present state X=0 X=1 Output
A D B 1
B A D 0
C C C 0
D B A 1
10. Design a 1011 sequence detector using JK flip-flop.
Distinguish Moore and Mealy machines with an example.