Hall Ticket No Question Paper Code: AEC002
INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
B.Tech III Semester End Examinations (Regular) December, 2017
Regulation: IARE R16
DIGITAL SYSTEM DESIGN
(Electronics and Communication Engineering))
Time: 3 Hours Max Marks: 70
Answer ONE Question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
UNIT I
1. Perform the following.
i. (988:85)10
ii. (11101010:01011)2
Distinguish between weighted and non-weighted codes with suitable example.
2. Generate a 7 bit odd parity Hamming Code for the given 4 bit data word 1101.
Perform the following.
i)10101001-10010011 using complement method
subtraction using complement method.
UNIT II
3. Discuss the properties of Boolean algebra.
Design the combinational logic circuit to convert BCD code to Excess-3 code and draw the circuit
diagram using minimum number of NAND gates only.
4. Define combinational logic circuit. Design 3-bit parity generator/checker (output is high for odd
number of inputs and low for even number of inputs) using NOR gates only.
Use Quine-Mcluskey minimization technique, obtain the minimal sum expression for the Boolean
function f
P
10; 13)
P
d 11; 15)
UNIT III
5. Write the truth table for a binary full subtractor function and obtain the irredundant disjunctive
normal expressions for the function. Show how the function could be realized using minimum
number of NAND gates.
Design 4-bit carry look ahead adder network and write its important merits.
6. Design an EX-OR and EX-NOR Gate using NAND Gates
Describe the 4-bit serial adder using full adder with block diagram and illustrate with example.

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UNIT IV
7. Explain the operation of Master slave JKFF using logic circuit, function table and timing diagram.

Draw the logic diagram for 4-bit universal shift register to perform the following operations,
illustrate this register operation with suitable example.
MODE OPERATION
s1 s0
0 0 Hold
0 1 Shift Left
1 0 Shift Right
1 1 Parallel Load
8. State and Derive the characteristic eqations for TFF, SRFF and JKFF.
Design a MOD-5 Synchronous counter using clocked D-FF for the sequence .…

UNIT V
9. Design Mealy sequential network for the following sequence, output is high for non zero present
state when input x using edge triggered JKFF. 0 1 2 for x 0 2 1 for x

Construct the excitation table, transition table, state table and state diagram for the Moore
sequential circuit expression
JA KA BX; JB KB A X and output Y A
10. Describe Mealy and Moore sequential circuit models with neat block diagrams. Compare.
Design a Moore type sequence detector to detect a serial input sequence of 101.