Exam Details
| Subject | digital system design | |
| Paper | ||
| Exam / Course | b.tech | |
| Department | ||
| Organization | Institute Of Aeronautical Engineering | |
| Position | ||
| Exam Date | July, 2018 | |
| City, State | telangana, hyderabad |
Question Paper
Hall Ticket No Question Paper Code: AEC002
INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
Four Year B.Tech III Semester End Examinations (Supplementary) July, 2018
Regulation: IARE R16
DIGITAL SYSTEM DESIGN
Time: 3 Hours Max Marks: 70
Answer ONE Question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
UNIT I
1. Generate a 7 bit odd parity Hamming Code for the given 4 bit data word 1101.
Convert the following into Gray Code
i. (3A8)16
ii. (578)8
2. Convert the following Binary numbers to Decimal and then to Hexadecimal.
i. 1010
ii. 1011.11
iii. 1101101
Distinguish between weighted and non-weighted codes with suitable example.
UNIT II
3. State and prove the De-Morgans theorem.
Solve(Simplify) the following Boolean equation Using Quine-McClusky technique
4. Define canonical form? Translate the following expressions into canonical form:
f a0bc a0c bcd
ii) F (x0 y0) z0)
Get the minimized sum-of products expression for N f
Q
with
don't cares: Q
X 11; 12; 13; 14; 15) Use Karnaugh map for simplification and write PIs and
EPIs.
UNIT III
5. Implement a Full Subtractor using Half Subtractor and one OR Gate
Design a 4 bit BCD to Excess-3 Code Converter using Logic gates.
6. Design a 4 Bit Prime Number Detector using Logic gates
Describe the 4-bit serial adder using full adder with block diagram and illustrate with example.
Page 1 of 2
UNIT IV
7. Draw the circuit diagram of T Flip-Flop using NAND gates and exaplain its operation with the
help of functional table.
Design a Mod-12 Asynchronous Counter using J-K-Flip-Flop
8. Convert D Flip-Flop to J-K Flip-Flop
With the help of logic Diagram and Functional Table explain the operation of 4-bit Bidirectional
Shift Registers
UNIT V
9. Explain Mealy and Moore models with general block diagrams.
Design a Mealy type sequence detector to detect a serial input sequence of 101.
10. Construct the excitation table, transition table, state table and state diagram for the Mealy
sequential circuit shown.
Design Moore sequential network for the following sequence, output is high for non zero present
state irrespective of the x input using edge triggered JKFF. 0 1 2 0 for the input
0 2 1 0 for the input x=0.
INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
Four Year B.Tech III Semester End Examinations (Supplementary) July, 2018
Regulation: IARE R16
DIGITAL SYSTEM DESIGN
Time: 3 Hours Max Marks: 70
Answer ONE Question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
UNIT I
1. Generate a 7 bit odd parity Hamming Code for the given 4 bit data word 1101.
Convert the following into Gray Code
i. (3A8)16
ii. (578)8
2. Convert the following Binary numbers to Decimal and then to Hexadecimal.
i. 1010
ii. 1011.11
iii. 1101101
Distinguish between weighted and non-weighted codes with suitable example.
UNIT II
3. State and prove the De-Morgans theorem.
Solve(Simplify) the following Boolean equation Using Quine-McClusky technique
4. Define canonical form? Translate the following expressions into canonical form:
f a0bc a0c bcd
ii) F (x0 y0) z0)
Get the minimized sum-of products expression for N f
Q
with
don't cares: Q
X 11; 12; 13; 14; 15) Use Karnaugh map for simplification and write PIs and
EPIs.
UNIT III
5. Implement a Full Subtractor using Half Subtractor and one OR Gate
Design a 4 bit BCD to Excess-3 Code Converter using Logic gates.
6. Design a 4 Bit Prime Number Detector using Logic gates
Describe the 4-bit serial adder using full adder with block diagram and illustrate with example.
Page 1 of 2
UNIT IV
7. Draw the circuit diagram of T Flip-Flop using NAND gates and exaplain its operation with the
help of functional table.
Design a Mod-12 Asynchronous Counter using J-K-Flip-Flop
8. Convert D Flip-Flop to J-K Flip-Flop
With the help of logic Diagram and Functional Table explain the operation of 4-bit Bidirectional
Shift Registers
UNIT V
9. Explain Mealy and Moore models with general block diagrams.
Design a Mealy type sequence detector to detect a serial input sequence of 101.
10. Construct the excitation table, transition table, state table and state diagram for the Mealy
sequential circuit shown.
Design Moore sequential network for the following sequence, output is high for non zero present
state irrespective of the x input using edge triggered JKFF. 0 1 2 0 for the input
0 2 1 0 for the input x=0.
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