Master of Science II (Electronics Communication Science)
Examination: Oct /Nov 2016 Semester IV (New CGPA)
SLR No. Day
Date Time Subject Name Paper No. Seat No.
SLR SJ-
359
Thursday
17/11/2016
02.30 PM
to
05.00 PM
VLSI Design
C
XIII
es Instructions: Question No. 1 and 2 is compulsory.
Attempt any three questions from Q.no. 3 to Q. no. 7
Figures to right indicate full marks.
Total Marks: 70
Q.1 Choose correct alternative. 06
The major disadvantage of custom design approach is:
Smallest chip area Closest match of
specification with customer
requirement
Longest time to market Lowest design cost.
For NMOS inverter minimum Pull up to Pull down ratio Zpu/Zpd:
1 4
8 2
The Dynamic power dissipation in CMOS inverter
Remains always zero
Is some value independent of frequency
Decreases with increasing frequency
Increases with increasing frequency
As clock input in a D-latch goes high
The Q output will be high
The latch becomes transparent
The Q output will be Low
The latch goes in storage mode.
In a ripple carry adder the each Full adder
Waits till the carry bit is calculated from the previous full adder
Completes operation simultaneously
Has no propagation delay
Does not have sum and carry outputs
The correct order of design steps is
Schematic entry, logic Synthesis, Simulation, Implementation
Logic Synthesis, Schematic entry, Simulation, Implementation
Simulation, Schematic entry, Logic Synthesis, Implementation
Schematic entry, Logic Synthesis, Implementation, Simulation
Page 1 of 2
State true/ false 08
The standard cells are fixed-height, variable-width cells.
Logical effort is a technique to estimate delay in a CMOS circuit.
A transmission gate uses CMOS transistor only.
EEPROM should be removed from the board for reprogramming
Synchronous clocking does not allow design automation
PSoC or programmable system-on-chip is offered by Cypress
Super MOS circuits decrease effect of channel length modulation
An analog-to-digital converter is a mixed-signal circuit.
Q.2 Write short note on the following:
Linear Voltage Current Converters 05
Schematic entry and Logic Synthesis 05
Transmission gates 04
Q.3 Answer the following:
Explain the ASIC design flow. 10
Why array based implementation of digital ICs is preferred? 04
Q.4 Answer the following:
Draw neat diagram of CMOS inverter and explain the VTC. How is the noise
margin estimated and optimized?
08
Explain the detailed design process for n-bit SIPO and SISO shift registers.
How is it converted into ring oscillator?
06
Q.5 Answer the following:
Explain the Lay out design of a CMOS gate. Estimate the area associated with
a 2-input NAND gate.
08
How is a Combinational Logic Cell designed? Explain with example of a
digital multiplexer.
06
Q.6 Answer the following:
State important feature of SPARTAN 6 FPGAs. How is it programmed? 08
How does the Analog and Mixed Signal design distinguish from the Digital
design? Which one of them is more complex? Why?
06
Q.7 Answer the following:
How are the thermal and humidity sensors interfaced to ASICs? 10
Explain operation of Nyquist rate A/D converters. 04