M.Sc. (Electronic Science) (Semester-IV) Examination, 2017
VLSI Design
iI
Day Date: Wednesday, 19-04-2017 Max. Marks: 70
Time: 02.30 PM to 05.00 PM
N.B. Q. 1 and Q.2 are compulsory.
Attempt any three from Q.3 to Q.7
All questions carry equal marks.
Use of nonprogrammable calculator is allowed.
Q.1 Choose the correct alternatives. 08
1g) located at the intersection of the vertical and
horizontal channels.
CLBs Switch boxes
Vertical connection box None of these
is fully customized to highest performance and
smallest size.
Semi
custom
Gate array Full custom FPGA
The carry generator in carry look ahead can be expressed
using gate
AND OR NOR XOR
The of a cell is usually kept low to avoid driving
problems.
Fanout fanin
input impedence all of the above
An antifuse is normally an open circuit until you force a
programming current through it about
15 5 Less than 15 Greater than 15
In CMOS circuits, which type of power dissipation occurs due
to switching of transient current and charging discharging of
load capacitance?
Dynamic dissipation Static dissipation
Both a and b None of these
In 3:8 decoder the number of inputs
2 1 8 3
CMOS operates more reliably than TTL in a high-noise
environment because of
Lower noise margin Smaller power
dissipation
High input impedance Higher noise margin
Page 1 of 2
State true or false. 06
A Transmission Gate is a complementary CMOS switch.
In dynamic logic the second phase, when Clock is high, is
called the setup phase.
Gate array implementation requires a two-step manufacturing
process.
We write indices of logic cell in ascending order.
To compensate, we make the shape factor, of the pchannel
Transistor in an inverter about twice that of the n
channel transistor.
Use heavy lines point wide) with a stroke to denote a data
bus and regular lines (0.5 point) to denote the control signals.
Q.2 Answer the following: 14
Write a note on a shift register 05
Explain standard cell based design 05
CMOS inverter logic structure 04
Design a one bit magnitude comparator. 04
Q.3 What do you mean by logic cell? Explain the sequential logic cell
in detail.
08
Explain ASIC design flow. 06
Q.4 What are the implementation strategies for digital ICs? Explain
semi custom design style in brief.
08
Explain the datapath logic cell. 06
Q.5 Explain briefly the DC analysis and voltage transfer
characteristics of CMOS inverter.
08
Distinguish between dynamic and static CMOS. 06
Q.6 What is the difference between fuse and antifuse? Explain
antifuse in detail.
08
What is a decoder? Design 3 to 8 line decoder. 06
Q.7 Explain in detail the super MOS transistor. 08
Explain NMOS inverter. 06