M.Sc. (Semester IV) (CBCS) Examination Nov/Dec-2018
Electronics Science
VLSI DESIGN
Time 2½ Hours Max. Marks: 70
Instructions: Q.1 and Q.2 are compulsory.
Attempt any three questions from Q. 3 to Q.7.
All questions carry equal marks.
Use of nonprogrammable calculator is allowed.
Q.1 Select the correct alternatives:- 08
Full custom ICs can operate at and require the
Lowest speed, largest die area
Lowest speed, smallest die area
Highest speed, smallest die area
Highest speed, largest die area
The is the most popular standard logic device family today.
TTL CMOS
ECLD None of the above
The design flow (in Y chart) starts from the that describes the
behavior of the target chip.
Algorithm Finite State Machine
Module description Chip floor plan
Realization of the circuit in the form of a netlist is done in
design step.
Logic Functional
Circuit Physical
AOI221 cell performs the function Z


The conversion of the netlist into its geometrical representation is done
in step.
Functional design Circuit design
Logic design Physical design
CPLD means
Complex programmable logic device
Complex programmable logic design
Circuit programmable logic device
Complex programmable level device
VLSI device has a circuit complexity of equivalent gate.
100-1000 10000-99,999
1000-10000 10-100
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Q.1 State true and false: 06
The cells in a FPGA may contain registers, look-up tables and memory.
All indices in the logic cell name greater than 1 correspond to the inputs
to the first "level" or stage the AND gate(s) in an AOI cell.
The n-channel stack implements the strong of the function and the
p-channel stack provides the strong
In a CMOS inverter, when the input is logic-high, the pMOS device is
ON and the nMOS device is OFF.
Each cell layout is designed with a fixed height, so that a number of
cells can be abutted side-by-side to form rows.
Aletra MAX 5000 EPLDs and Xilinks EPLDs both uses UV optically
programmable read only memory (OPROM).
Q.2 Attempt the following.
Write a note on Logical effort. 05
What is super buffers? 05
Write a note on static RAM? 04
Q.3 What are the different types of ASIC? Explain the full custom design style. 08
Explain VLSI design flow. 06
Q.4 What do you mean by inverter? Explain the DC analysis and voltage
transfer characteristics of CMOS Inverter.
10
What is a propagation delay? 04
Q.5 What do you mean by logic cell? Explain the combinational logic cell. 08
What is comparator? Design a 2-bit comparator. 06
Q.6 Explain the EPROM and EEPROM technology. Describe how those are
different from each other.
08
Write a short note on metal-metal antifuse. 06
Q.7 Explain how CMOS based two stage Op-Amp circuit can be realized in
practice.
10
Compare between full custom and semi custom design style. 04