M.Sc. (Semester II) (CBCS) Examination Mar/Apr-2018
Electronic Science
DIGITAL ELECTRONICS AND VHDL
Time 2½ Hours
Max. Marks: 70
Instructions: Q.1 and Q.2 are compulsory. Attempt any three questions from Q. 3 to Q.7. All questions carry equal marks. Use of nonprogrammable calculator is allowed.
Q.1

Select the correct alternatives:-
08
Which logic level is not supported by verilog?
U
X
Z
None of the above
Verilog supports dimensional array of registers, integers, nets or times.
one
two
three
both a and b
The may execute in non-zero simulation time.
function
task
both a and b
none of these
Which among the following is/are identical in Mealy and Moore machines?
Combinational output signal
Clocked process
Both a and b
None of the above
Which operators has highest precedence in Verilog?
Unary
Multiplication
Addition
Conditional
How may stable state/states present in flip-flop?
2
6
0
8
Which among the following are used in programming array logic for reducing the loading on inputs?
Output buffers
Input buffers
OR matrix
AND matrix
Enable input of shift register is called a
load
store
reset
strobe
Q.1

State true and false
06
Gate-level modeling is virtually the lowest-level of abstraction.
A ring counter is a type of combinational logic circuits.
Each square in a karnaugh map represents a maxterm.
The repeat loop block continuously executes the block for a given number of times.
Binary counter that counts incrementally and decremently is called up counter.
A blocking assignment statement is executed in the order they are specified in a sequential block.
Q.2
Attempt the following:-
Mention the advantages and disadvantages referred to PAL.
05
Design a full adder with its truth table.
05
Briefly explain lexical conventions in Verilog.
04
Q.3

Design 3:8 decoder and draw its logic diagram.
08
B)What is ripple counter?
06
Q.4
A)Design a 2-bit comparator with its truth table.
08
B)Explain state table reduction and state assignment technique using the state table given below:
Q.5
A)Design and implement a full adder using Verilog HDL with gate level modeling (use half adder).
10
B)Write a Verilog code for 8-bit binary counter using behavioral modeling.
04
Q.6
A)Explain in detail behavioral modeling in Verilog with suitable example.
10
B)Write a short note on shift registers.
04
Q.7
A)Draw an architecture of CPLD and explain in brief.
08
B)Write a Verilog HDL code for 2:4 decoder using data flow modeling.
06