M.Sc.(Electronic Science)(Semester II) Examination, 2017
Digital Electronic of VHDL (HCT 2.2)
Day Date: Friday, 21-04-2017 Max. Marks: 70
Time: 10.30 AM to 01.00 PM
N.B. are compulsory.
Answer any three questions from Q3 to Q.7.
All questions carry equal marks.
Use of nonprogrammable calculator is allowed.
Q.1 Select the correct alternative: 08
The beginning and end of a loop in a Verilog is defined as
Begin---end Curly brackets
None of these Both a and b
Verilog supports array of registers, integers,
nets or times.
One Two Three Both a and b
The statement is used to make a decision
whether a statement is executed or not.
while If-else for repeat
How many flip -flops are required to produce a divide -by-256
device?
1 4 8 7
The high impedance state or floating state in verilog is
1 X Z Both X and Z
How many stable state/ states present in flip-flop?
2 3 0 4
Once a PAL has been programmed
It cannot be reprogrammed
Its output are only active HIGH
Its outputs are only active LOW
its Logic capacity is lost
In Tb flip-flop when state of T flip-flop has to be complemented, T
must
0 1 T T+1
Page 1 of 2
Q.1 State True or False: 06
Verilog is case sensitive.
A combinational logic circuit is one whose output depends on
current as well past input
Modules communicate with external world using ports.
Verilog synthesizers with the white space and carriage returns
differently.
Data flow modeling is low level of abstraction as compared to
behavioral modeling.
Flip-flop stores I bit information.
Q.2 Attempt the followings.
With a neat block diagram, explain Mealy and MOORE models. 05
Design half adder and draw its truth table. 05
Compare: encoder and decoder. 04
Q.3 Design Carry look ahead adder and draw its logic diagram. 08
Distinguish between tasks and functions. 06
Q.4 Design 4-bit Johnson counter using J-K flip flop with its timing diagram. 08
Explain state table reduction and state assignment technique using the
state table given below.
14
Present
State
Next State Output(Z)
Input Input
X=0 X=1 X=0 X=1
A A B 0 0
B D C 0 1
C F E 0 0
D D F 0 1
E B G 0 0
F G C 0 1
G A F 0 0
06
Q.5 Write a Verilog code for the following using behavioral modeling style. 10
3:8 decoder
ii) 4-bit binary adder
Write a Verilog code for 4:1 multiplexer using case statement. 04
Q.6 Explain in detail operators in Verilog. 08
Design a PLA to realize the following three logic function and show the
internal connections.
06
f1
A'.B.E B'.C.D'.E

Q.7 What is FPGA? Explainthe working of its different blocks with a neat
diagram.
08
Write a Verilog HDL code for S-R flip-flop using gate level modeling 06