M.Sc. (Semester II) (CBCS) Examination Nov/Dec-2018
Electronics Science
DIGITAL ELECTRONICS AND VHDL
Time: 2½ Hours Max. Marks: 70
Instructions: Q.1 and Q.2 are compulsory
Answer any three questions from Q.3 to Q.7.
All questions carry equal marks.
Use of nonprogrammable calculator is allowed.
Q.1 Select the most correct alternative 14
Verilog HDL originated at
AT&T Bell Laboratories
Defence Advanced Research Projects Agency (DARPA)
Gateway Design Automation
Institute of Electrical and Electronics Engineers (IEEE)
Once a PAL has been programmed,
cannot be reprogrammed outputs are only active HIGH
outputs are only active LOW logic capacity is lost
Bubbled OR gate is equal to
NAND gate AND gate
Ex-OR gate NOR gate
Odd parity of word can be conveniently tested by
XOR gate OR gate
AND gate NOT gate
The number of two input multiplexes required to construct a 210 input
multiplexer is
31 10
127 1023
The characteristic equation of D flip-flop is
Q=1 Q=0
Q=Dbar Q=D
RTL stands for
Resistor-transfer logic Register-transistor logic
Register-transfer logic None of these
For describing circuits like flip flops, statement is used.
Always Entity
Component Process
Verilog supports dimensional array of registers, integers, nets or
times.
one two
three both a and b
10) The may be executed in non-zero simulation time.
Function Task
Both a and b None of these
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SLR-VH-238
11) Which among the following is/are identical in Mealy and Moore
machines?
Combinational output signal Clocked process
Both a and b None of these
12) Which operator has highest precedence in Verilog?
Unary Multiplication
Addition Conditional
13) Memory unit is not required in circuits.
Sequential Combinational
Both a and b Simple circuits
14) The number of state in FSM is
Infinite Finite
20 23
Q.2 Answer the following.
What is Verilog and explain the various modeling used in Verilog? 05
Design 4:1 multiplexer and draw its truth table. 05
What is state diagram? 04
Q.3 Explain the basic gate primitives in Verilog HDL with details? 10
Write a Verilog program for 4-to-16 decoder. 04
Q.4 Design a 4-bit Johnson counter using J-K flip flop with its timing diagram. 08
Explain state table reduction and state assignment technique using the
state table given below.
Present State
Next State Output
Input Input
X 0 X 1 X 0 X 1
A A B 0 0
B D C 0 1
C F E 0 0
D D F 0 1
E B G 0 0
F G C 0 1
G A F 0 0
06
Q.5 Design a 2-bit asynchronous up counter using T flip flop with its timing
diagram.
10
Design half adder using K map and realize it using basic gates. 04
Q.6 Design and write a Verilog program for 4 bit binary adder. 10
Write a Verilog program for 3:8 decoder? 04
Q.7 Draw the architecture of CPLD explain them in brief. 08
f1 E A′ . B′ . D′ B′ . C. D′ A′ . B. C.D. E′
f3 E A′ . B′ .D′ B′ . C′ .D′ . E A′ . B. C.D