M.Sc. (Semester III) (CBCS) Examination Oct/Nov-2017
Electronics
CMOS ANALOG CIRCUIT DESIGN
Day Date: Saturday, 25-11-2017 Max. Marks: 70
Time: 02.30 PM to 05.00 PM
Instructions: Q no. 1 Q. no. 2 are compulsory.
Attempt any three questions from Q. no. 3 to 7
Attempt five questions.
Figures to the right indicates full marks.
Q.1 Choose the correct Answer: 08
The clock and for switched capacitor resistor emulation should
be
Non-overlapping in phase
Non-overlapping out of phase
Overlapping in phase
Overlapping out of phase
In case of nMOS transistor, for current conduction the drain must be

Floating Negative
Positive All of these
If gates of the two MOS transistors are applied to the same potential
and drains are also connected to one same power supply, then
current through one device is 4.35 mA. What is current through
another MOS device?
4.35mA 9.15 mA
17mA All of these
In CMOS current amplifier, which of the following statement is
correct?
Input impedance is ultra high.
Output impedance is very low
Input impedance is high and output impedance is low
Input impedance is low and output impedance is high.
For nMOS transistor, the drain current in saturation region is given
by
− − −
− − −
compensation is used to minimize the output swing
effect.
Miller capacitor Miller resistor
Folded transistor All of these
Page 2 of 2
SLR-E-32
Which of the following is true for Parallel capacitor Switched
Capacitor circuits?
Av CixCF Av CF/Ci
Av Ci/CF Av RFxRi
To ensure active load to the nMOS amplifier is
configured.
PMOS device NMOS device
BiCNOS device CMOS device
State true or false: 06
If two identical MOS devices are used to design voltage divider
circuit, then resultant voltage at the collector will be Vdd/2.
Channel between source and drain will be formed if Vgs VT.
If gate of NMOS device is connected to drain, then it acts as active
resistor.
The switched capacitor amplifier is the realization of continuous time
domain circuit.
Differential amplifier stage of CMOS Operational amplifier is called
voltage to current convertor stage.
BiCMOS transistor is suitable for low frequency applications.
Q.2 Attempt any two of the following: 10
Write a note on parasitic capacitors appeared in MOS devices.
What do you mean by channel width modulation?
Mention the steps involved in fabrication of MOS transistor in n-well
technology.
Describe the designing of current source circuit. 04
Q.3 Describe different load circuits for CS amplifier. 08
Describe in detail, switched capacitor integrator circuit. 06
Q.4 With the help of block diagram explain the CMOS operational amplifier. 08
Describe folded cascode operational amplifier. 06
Q.5 Give the principle of Switched capacitor. Derive the expression for
resistance value by emulation of switched capacitor.
08
Describe in detail, switched capacitor summing amplifier. 06
Q.6 With suitable diagram explain mechanism in nMOS device. Derive
expression for drain current.
08
Write a note on current mirror circuit. 06
Q.7 Describe large signal model of CS MOS amplifier. 08
Describe in detail, use of MOS device as a diode, resistive divider
biasing circuit.