M.Sc. (Semester III) (CBCS) Examination Nov/Dec-2018
Electronics
CMOS DESIGN TECHNOLOGIES
Time: 2½ Hours Max. Marks: 70
Instructions: All questions are compulsory.
Use of Log table and calculator is allowed.
Draw neat and labeled diagram wherever necessary.
Figures to the right indicate full marks.
Q.1 Choose the correct answer: 14
The polysilicon layer is represented by colour.
Red Green
Yellow Light blue
Twin tube process uses for protection against latch-up.
guard rings poly layer
sapphire layer epitaxy layer
In VLSI design components of design are commonly called as
cells tools
footprints constraints
In polysilicon interconnect is used as gate material.
Silicon Silicide
Tantalum All of these
The basic rule of charge sharing is
Cb>10 Cs Cs >10 Cb
Cb >100 Cs Cs >100 Cb
SOI process is advantageous because it does prevent
Body effect problem Filed inversion problem
Latchup problem All of these
Absolute value of threshold voltage decreases with an in
temperature.
Decrease Increase
Constant None of these
In PMS design environment P stands for
Parameter Progress
Process Processor
power dissipation occurs due to current continuously drawn from
power supply.
Total Dynamic
Static Short circuit
10) Which of the following does affect the circuit's behavior?
Temperature Supply voltage
Both and Design tools
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11) N-well CMOS process start with lightly dopped
n-type substrate p-type substrate
sapphire layer polysilicon layer
12) In standard cell based design process connects the modules with
wires.
placement floor planning
routing none of these
13) In MOS transistor current in the channel can be modulated by
voltage applied to gate voltage applied to drain
voltage applied to source all of these
14) The basic raw material used in CMOS fabrication is
disk of silicon wafer of silicon
both and ingots of silicon
Q.2 Attempt any four of the following questions. 08
Draw physical structure of nMOS transistor.
Explain Id-Vds relation.
Explain pull- up to pull down ratio.
Explain enhancement and depletion modes of MOS transistor.
Explain parasitic components in CMOS process.
Write a note on. (Any Two) 06
Write a note on transmission gate.
Write a note on βn/βp ratio.
Write a note on interconnects.
Q.3 Answer any two of the following questions. 08
Describe different characteristics of digital electronic design.
Obtain MOS device design equation.
Explain I/O structures.
Answer any one of the following questions. 06
Explain n-MOS enhancement transistor in detail.
Explain basic steps involved in CMOS fabrication processes.
Q.4 Answer any two of the following questions. 10
Explain latchup in detail.
Discuss general issues in design representation.
Draw stick diagram for NAND gate.
Answer any one of the following questions 04
Describe CAD design flow.
Explain Y-diagram.
Q.5 Answer any two of the following questions. 14
Explain DC characteristics of CMOS inverter.
Explain basic n-well CMOS process of fabrication.
Draw stick diagram for two input multiplexer.