Master of Science I (Electronics Communication Science)
Examination: Oct/Nov 2016 Semester II (Old CGPA)
SLR No. Day
Date Time Subject Name Paper
No. Seat No.
SLR SJ
348
Thursday
24/11/2016
10:30 A.M
to
01:00 P.M
Digital Design and VHDL
Programming
C
VIII
Instructions: Q.No.1 and 2 are compulsory.
Answer any three questions from Q.No.3 to Q.No.7.
All questions carry equal marks.
Use of non programmable calculator is allowed.
Total Marks: 70
Q.1 Select correct alternatives: 06
In a VHDL code statement is used in architecture having
behavioural description.
Process Case
Generate Wait
is a logic circuit which generates the parity bits for even parity or
odd parity.
Parity generator Parity checker
Comparator Adder
A MOD-2 counter followed by a MOD-5 counter is
Same as MOD-5 counter
followed by a MOD-2 counter
A decade counter
A MOD-7 counter None of these
Generics are specified only in
Entities Architectures
Process Library
Which among the following constraint/is/are involved in a state- machine
description?
State variable clock
State transitions output specifications
Reset condition
All of the above
Which basic logic gates are cross coupled to construct a basic S-R-flip-flop?
AND or OR gates AND or NOR gates
NOR or NAND gates XOR or XNOR gates
Page 1 of 2
State True or false: 08
The number of states in FSM in infinite.
Sequential system exhibits the necessity for the existence of at least one
feedback path from output to input.
Bit-vector type is pre-defined in the standard package as one-dimensional
array type comprising each element of BIT type?
QFP CPLD packaging can provide maximum number of pins on the package
due to small size of the pins?
In delta delay, output follows any changes in input.
Every entity can have two architectures.
The fast carry or look-ahead carry circuits found in most 4 bit parallel-adder
circuits is used to reduce propagation delay.
Decoder method of combination circuit implementation is widely adopted
with maximum output functions and minimum requirement of ICs.
Q.2 Attempt the following:
Write a short note on generate statement. 05
Explain the attributes of VHDL. 05
Compare: Multiplexer and De-multiplexer 04

Q.3 Explain the following:
Entity
Architecture
Library
10
Explain the difference between variable and signal? 04
Q.4 Design 4-bit J Johnsons counter using J-K flip flop with its timing diagram. 08
Implement the function using PLA. f1=Σ m f2=Σ m 06
Q.5 What is a decoder? Write the VHDL code for 3:8 decoder and draw its truth table
also.
08
Write the VHDL code for 4:1 multiplexer. 06
Q.6 Design parity generator using K map and draw its logic diagram. 08
Explain operator overloading with a suitable example. 06
Q.7 Draw architecture of altera Flex10 K and explain in brief. 10
Write a VHDL code for half adder. 04