F.Y. M.Tech. (Electronics Engineering) (Semester (New CBCS)
Examination, 2018
digital design and verification
Day and Date Tuesday, 4-12-2018 Total Marks 70
Time 10.00 a.m. to 1.00 p.m.
Instructions All questions are compulsory.
Assume suitable data if necessary.
section i
1. Attempt any two of the following
E xplain and compare the direct testing method and constrained random
stimulus for testing the design.
E xplain the communication between the testbench and DUT along with the
code for communicate with the port.
E xplain following array operations of system verilog along with suitable
example.
I For and foreach
II C opy and compare
2. Attempt any one of the following 5
E xplain FIFO memories with suitable application.
Write short note on Metastability.
3. Attempt following
Write verilog code for modeling D flip-flop. Also write the testbench for
testing it.
Write verilog code for modeling 4 bit parallel adder. Also write the testbench
for testing it.
Set P
section iI
4. Attempt following
What is IP What are the different forms of IP Explain in brief.
Write note on Use of External Hard IP during prototyping.
5. Attempt any one of the following 7
What are wire load models Explain.
What is IR drop How to analyze IR drop Explain.
6. Attempt following
What are the coarse grained reconfigurable devices Explain any one type
in brief.
E xplain antifuse based FPGA in brief.