1
Seat No.: Enrolment
GUJARAT TECHNOLOGICAL UNIVERSITY
PDDC SEMESTER-VI EXAMINATION WINTER 2018
Subject Code:X61102 Date: 20/11/2018
Subject Name: VLSI Technology and Design
Time: 02:30 PM TO 05:00 PM Total Marks: 70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
Q.1

Define following terms.
Semi-custom Full custom Regularity Modularity Yield
Testability Locality
07

Draw and explain Y chart for VLSI design flow. Also draw VLSI design flow at different abstraction levels.
07
Q.2

Explain FPGA in brief.
07

Draw main fabrications steps for CMOS inverter with suitable labels.
07
OR

Explain NMOS with external bias with suitable diagrams.
07
Q.3

List second order effects for NMOS. Explain any two in details.
07

Write short note on MOS capacitance.
07
OR
Q.3

Draw and explain resistive load inverter. Also draw VTC of it.
07

Draw and explain VTC of CMOS inverter. Also list advantages of CMOS technology.
07
Q.4

Derive the equation of TPLH for CMOS inverter.
07

Explain CMOS ring oscillator with suitable diagrams.
07
OR
Q.4

Draw CMOS circuit for JK flip-flop.
07

Explain CMOS transmission gate with suitable diagrams.
07
Q.5

Explain voltage bootstrapping in dynamic logic circuits.
07

Write a short note on Domino CMOS.
07
OR
Q.5

Discuss the on-chip clock generation and distribution for a VLSI chip.
07

Explain latch-up problem in CMOS circuits. Also list its precautions.
07