1
Seat No.: Enrolment
GUJARAT TECHNOLOGICAL UNIVERSITY
PDDC SEMESTER- VI • EXAMINATION SUMMER-2017
Subject Code: X61102 Date: 02/05/2017
Subject Name: VLSI Technology and Design
Time: 10.30AM to 01:00PM Total Marks: 70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
Q.1 Draw and explain Y chart fort VLSI Design flow. Also draw simplified VLSI
design flow at different abstraction levels.
07
List and explain importance of different CAD tolls used for VLSI design. 07
Q.2 Explain n-well CMOS fabrication with necessary diagrams. 07
Define design rules for layout design in VLSI Technology. List and explain
types of design rules. Draw layout of CMOS inverter with necessary
information.
07
OR
Explain latch-up and its prevention in CMOS technology. 07
Q.3 Derive drain current equation in linear region and saturation region for NMOS. 07
Define scaling in VLSI Technology. 07
OR
Q.3 Explain on chip clock generation and distribution. 07
Explain difference between FPGA and CPLD. 07
Q.4 A CMOS inverter has VTO,n 0.8 VTO,p 0.8 V and kn=kp. Obtain VIL,
VIH, VOH,VOL NMH and NML for VDD 5v .
07
A CMOS inverter has cox 120 V2 cox 60 V2 VTO,n 0.8
VTO,p 1.0 TPHL 0.2 ns TPLH 0.15 ns VDD 3v Cload 300 ff
Determine and
07
OR
Q.4 Draw CMOS implementation for following Boolean equation
Assume that 10 for all NMOS and =15 for all PMOS. Find
equation for NMOS and PMOS.
07
Draw and explain SR flip flop using CMOS Technology. 07
Q.5 Write short notes on built in self test techniques. 07
Explain Basic Principles of pass transistor circuits. 07
OR
Q.5 Explain CMOS Dynamic Circuit Techniques. 07
Write short notes on Adhoc Testable design techniques. 07