Exam Details

Subject digital principles and system design
Paper
Exam / Course b.tech
Department
Organization SETHU INSTITUTE OF TECHNOLOGY
Position
Exam Date May, 2017
City, State tamil nadu, pulloor


Question Paper

Reg. No.
B.E. B.Tech. DEGREE EXAMINATION, MAY 2017
Second Semester
Computer Science and Engineering
01UCS207- DIGITAL PRINCIPLES AND SYSTEM DESIGN
(Common to Information Technology)
(Regulation 2013)
Duration: Three hours Maximum: 100 Marks
Answer ALL Questions.
PART A (10 x 2 20 Marks)
1. Convert (101101.1101)2 to decimal and hexadecimal form?
2. What are the limitations of K map?
3. Write down the truth table of a full subtractor.
4. Obtain the truth table for BCD to Excess code converter.
5. Distinguish between a decoder and a demultiplexer.
6. Compare SRAM and DRAM.
7. Derive the characteristic equation of a JK flip flop.
8. What is a primitive flow table?
9. Define race condition.
10. Define hazards and its types.
PART B x 16 80 Marks)
11. Reduce the following function using K-map technique and implement the reduced Boolean expression with basic gates
M 10, 12, 14) d 6).
Question Paper Code: 31227
2
31227
Or Minimize the expression using Quine McCluskey method (Tabulation) method 15, 24, 29, 11, 31).
12. Design a circuit that converts 8421 BCD code to Excess 3 code. Or Design a full adder circuit with necessary diagram. Write the HDL description of the circuit specified by the following Boolean function. 13. Implement the following Boolean function using a 8 to 1 multiplexer ACD+ Also implement the function using 16 to 1 multiplexer. Or Implement the following function using PLA: B(x
14. Design a synchronous counter which counts in the sequences 000, 001, 010, 011, 100, 101,110, 111,000 using D-FF. Or Implement T flip flop using D flip flop and JK flip flop.
15. Design an asynchronous sequential circuit with input X1 and X2 and one output Z. Initially and at any time if both the inputs are output is equal to 0. When X1 or X2 becomes Z becomes 1. When second input also becomes The output stays at 0 until circuit goes back to initial state. Or
Implement the Switching Function 14, 15) by a static hazard free two level AND OR gate network.


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  • digital principles and system design
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