Hall Ticket No Question Paper Code: AEC019
INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
B.Tech IV Semester End Examinations (Regular) May, 2018
Regulation: IARE R16
DIGITAL AND PULSE CIRCUITS
Time: 3 Hours Max Marks: 70
Answer ONE Question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
UNIT I
1. Generate a 7 bit even parity Hamming code for the given 4 bit message 1011 and rewrite the
entire message with Hamming code.
Simplify the following Boolean expressions to minimum no. of literals.
i. xy;
ii. xyz yyz z xy;
iii. b
iv. yz; xyz
2. Convert the following
i. 87710
ii. 408:9310
iii. ABC16
iv. 29210
Subtract the following using complement method.
i. 10112 10002
ii. 4610 1210
UNIT II
3. Design a 4 bit BCD to Excess-3 Code Converter and realize using logic gates.
Implement the following function using logic gates F
P
7).
4. What are the universal gates? Design a full adder using universal gates.
Using tabular method obtain the minimal expression for
F
P
d 11; 12; 13; 14; 15).
Page 1 of 2
UNIT III
5. Convert S-R flip-flop to J-K flip-flop and draw its logic circuit.
Draw the logic diagram of 4 bit ring counter using D flip flops and explain its operation with the
help of bit pattern.
6. Draw the logic diagram of a D flip flop and using excitation table, explain its operation.
Design a Mod-9 synchronous counter using T Flip-Flop with a neat sketch.
UNIT IV
7. Draw the circuit diagram of voltage series feedback and derive expressions for input resistance
and output resistance.
What are the types of feedback? Mention the characteristics of a Negative feedback amplifier.

8. With neat diagram, explain the working of Hartley oscillator using BJT and derive an expression
for frequency of oscillation.
What do you mean by oscillators and state the conditions for oscillations.
UNIT V
9. Draw the simplified h-parameter model of CE configuration and derive the expression for AI ;RI
Av and R0.
State and prove millers theorem and dual of millers theorem.
10. Draw the circuit diagram of Darlington emitter follower and derive an expression for AI ;RI ;Av
and R0.
Six identical stages are coupled, each amplifier having fl =100 Hz and fh 100 KHz. Determine
the overall upper cut-off frequency, the overall lower cut off frequency for the six stages. What
is cascading? derive the expression for AI ;RI .