Hall Ticket No Question Paper Code: BES005
INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
M.Tech II Semester End Examinations (Regular) July, 2017
Regulation: IARE-R16
FPGA ACHITECTURE AND APPLICATIONS
(Embedded Systems)
Time: 3 Hours Max Marks: 70
Answer ONE Question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
UNIT I
1. Explain the logic diagram of a typical sequential Programmable Array Logic, the 16R4.
Write a brief note on sharable expanders in CPLD.
2. Explain the structure of Read-Only Memory consisting of n-input lines and m-output lines.[7M]
Explain the architecture of Xilinx cool runner XCR3064XL CPLD.
UNIT II
3. Briefly discuss the desirable properties of technological Programmable Elements in FPGAs.
Explain the general structure of FPGA chip consisting of a large number of programmable logic
blocks surrounded by programmable I/O block.
4. Give the comparison among different programmable connections in FPGA.
Briefly discuss different applications of FPGAs.
UNIT III
5. Briefly discuss the features of different families XC3000-series FPGAs.
Explain the architecture of XC4000-series FPGA highlighting different programmable logic blocks.

6. Write a brief note on Static-RAM implementation of FPGA technology.
List the key features of XC2000-series FPGA architecture and explain different components of
XC2000-series FPGA architecture.
UNIT IV
7. Explain the features of anti-fuse programmed FPGAs.
Explain the implementation of an ACT 1 logic module using pass transistors.
8. Illustarte the routing architecture of an Actel ACT FPGA.
Briefly discuss the features of ACT-2 anti-fuse programmed FPGA.
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UNIT V
9. Explain the architecture of a full page high-resolution display video controller.
Explain the design flow for Actel synthesis.
10. Explain the concept of position tracking for a robot manipulator in controlling a high precision
robot with 16 degrees of freedom.
With the help of diagram explain the architecture of high-speed DMA controller.