Hall Ticket No:
Question Paper Code B3402
(AUTONOMOUS) M. Tech I Semester Supplementary Examinations, June 2017
(Regulations: VCE-R15) DIGITAL SYSTEMS DESIGN
(Digital Electronics and Communication Systems) Date: 07 June, 2017 AN
Time: 3 hours
Max Marks: 70
Answer any FIVE Questions
Each Question carries equal marks
1.
What are timing hazards? What are the types of timing hazards? What are the ways to design hazard free circuits?
7M
Design a combinational circuit that will give an output of when the given number N is a prime number and output is otherwise. Assume Maximum value of N is "1111".
7M
2.
Compare bipolar PLD and CMOS PLD with suitable diagrams.
7M
With the help of Pin diagram, truth table and block diagram explain the 74x139 decoder(dual 2 to 4 line).
7M
3.
Explain the operation of 74x148 Priority encoder with pin diagram, truth table and logic diagram.
7M
Draw the circuit for 1-bit comparator and explain the construction of 4-bit iterative comparator with algorithm and block diagram.
7M
4.
Discuss the steps involved in analyzing clocked synchronous state machines.
7M
Distinguish between mealy and moore logic circuits with block diagrams.
7M
5.
List out the steps involved in analysis of feedback sequential circuits and explain the same.
7M
Write VHDL code to generate clock signal of 10 MHz? How to write sequential circuit design in HDLs.
7M
6.
What are the steps in designing with FPGA? How is it different from ASIC design?
7M
Explain with an example the components of a state machine chart.
7M
7.
What is fault dominance and explain check point theorem.
7M
Explain the need for logical fault models in digital circuit testing. Discuss in detail the single stuck-at fault model and bridging fault model.
7M
8.
With an example explain the random testing method.
7M
With the help of flow chart, explain PODEM algorithm with neat diagrams.
7M