Hall Ticket No:
Question Paper Code B3402
(AUTONOMOUS) M. Tech I Semester Regular/Supplementary Examinations, December 2017
(Regulations: VCE-R15) DIGITAL SYSTEMS DESIGN
(Digital Electronics and Communication Systems) Date: 29 December, 2017 FN
Time: 3 hours
Max Marks: 70
Answer any FIVE Questions
Each Question carries equal marks
1.
Write behavioural style Verilog HDL program to detect 4-bit prime number. Design canonical sum of product circuit.
7M
Determine the minimal sum of products form for the following expression using K-Map method
7M
2.
Draw the general structure of a CPLD and explain how a logic function can be realized on CPLD with an example.
7M
Realize F1,F2 using PLA. Give the PLA table and connection diagram for
F1=Σm(
7M
3.
List out the advantages of carry look ahead adder and design 4-bit binary adder.
6M
Write behavioural style of Verilog HDL code for 8-input priority encoder with the help of truth table.
8M
4.
Explain the functional behavior of master slave JK flip flop with a neat sketch.
7M
Convert the following mealy machine into a corresponding moore machine
PS
NS, Output
A
B,0
E,0
B
E,0
D,0
C
D,1
A,0
D
C,1
E,0
E
B,0
D,0
7M
5.
Explain the reasons for clock skew and how it can be avoided.
7M
Write a behavioural style Verilog HDL code for positive edge sensitive D flip flop with asynchronous preset and clear.
7M
6.
Explain the difference between flowchart and SM chart with symbols.
6M
Draw an ASM chart to design control logic of a binary multiplier. Realize the same using multiplexer and encoder.
8M
7.
Explain the different faults presented in a combinational circuit with examples.
6M
Explain the procedure to find fault detection and location in a sequential circuits.
8M
8.
Explain how Kohavi algorithm is useful in the detection of circuits with example.
7M
Apply D-algorithm to detect h stuck at 0 fault in the given circuit and derive the test vectors.
Fig.1
7M