Hall Ticket No:
Question Paper Code B3203
(AUTONOMOUS) M. Tech I Semester Regular/Supplementary Examinations, January 2018
(Regulations: VCE-R15) COMPUTER ORGANIZATION AND ARCHITECTURE
(Computer Science and Engineering) Date: 02 January, 2018 FN
Time: 3 hours
Max Marks: 70
Answer any FIVE Questions
Each Question carries equal marks
1.
Design and explain a full adder and half adder using NAND gates.
7M
Minimize the following expressions using K-map method and write the circuit diagram using basic gates:
i. F 10) ii. F 13, 14, 15) 10,11) 7M
2.
Explain the different registers that are available in the processor of a digital computer and the connection between the processor and the memory.
7M
Explain the single bus structure and also explain how performance of the computer can be measured.
7M
3.
Explain the following addressing mode with suitable example:
i. Immediate Mode
ii. Indirect Mode
iii. Index Mode
iv. Autodecrement Mode
v. Register Mode
7M
Explain role of different computer registers with respect to instruction Fetch cycle and execution. Give example.
7M
4.
Using Booth algorithm multiply and
7M
Explain 4 bit carry-look ahead adder and use it to build a 12 bit carry-look ahead adder.
7M
5.
With the diagram, explain the basic organization of microprogrammed control unit.
7M
Illustrate micro instructions to execution of a complete instruction Add R1.
7M
6.
Explain the Internal Organization of Memory chips with a diagram.
7M
What is cache memory? What is locality of reference? With neat Diagrams explain the cache memory mapping functions.
7M
7.
Describe the input transfer on a synchronous bus with the detailed timing diagram.
7M
What is the role of a DMA (Direct Memory Access) controller? Explain DMA by providing the registers used.
7M
8.
Explain the principle characteristics of multiprocessors? List its advantages.
7M
Explain the concepts of shred memory in multiprocessors.
7M