1. Draw the logic diagram of a 4-bit look ahead carry adder and calculate the speed-up compared to a 4-bit binary ripple adder.

2. Reduce the state diagram shown in Figure 1 and also write the reduced state table. Consider the input sequence as "0 1 0 1 0 1 1 0 1 0 0" starting from the initial condition <img src='./qimages/8868-2.jpg'> <br><br>


3. Design the controller whose state diagram is shown in Figure 2. Write the RTL model of the controller. <img src='./qimages/8868-3.jpg'> <br><br>

4. Implement the Boolean function

F(A, 11, 14) and

P(A, IIM(l, 12, 15)

with multiplexer.

5. Write the working principle of ROM matrix for implementing a truth table of a full subtractor.

6.(a) Differentiate between Synchronous state machine and Asynchronous state machine. Design a Mod-6 up counter using J-K flip-flop.

7. Explain the types of operators in VHDL design. Write a program for a 4-bit binary to BCD conversion using data flow model.

8. Draw a multilevel NOR and multilevel NAND gate circuit to implement the Boolean function (AB CD)E BC B).

9. Write the data flow description for a 4-bit comparator. The output of the comparator when both the inputs are unequal and is for equal input.

10. Design a logic circuit that controls an elevator in a four-storied building. The circuit has two inputs for user to indicate the desired floor to reach. The lift starts moving when start input 1. M is an output signal that indicates if the desired floor is reached (i.e., M and stops the lift for opening of gate. remains in low state (i.e., when the lift is moving. F1 and F2 are two outputs to show the floor level that the lift has reached.