F.Y.M.C.A. (Part II) (Faculty of Engg.) Examination, 2016
MICROPROCESSOR
Day and Date Monday, 5-12-2016 Total Marks 100
Time 10.30 a.m. to 1.30 p.m.
Instructions Figures to the right indicate marks.
Q. 3 A and Q. 5 A are compulsory.
Write a program if necessary.
1. Multiple choice questions 20
Which interrupt has highest priority
TRAP INTR RST 7.5 RST 6.5
Which of the following units are used in 8085
Register ALU
Control All of the above
Maximum memory which can be connected with 8085
32 KB 1 KB 10 KB 64 KB
Which of the following is not the addressing mode in 8085
Register Direct
Indirect Implied
Which of the following is not logical instruction in 8085
RLC DAA STC CMC
Which of the following is not an example of 8085 instruction category
Data transfer Arithmetic and logic
Branching Cache memory transfer
Which of the following instruction is used to save accumulator contents on to
the stack
PSH PSW PUSH A
POP A None of the above
SLR-ER 13
What is the second machine cycle in ADD M instruction
Memory read Memory write
Idle machine No second machine cycle
How many times program counter is accessed in STA 2500H
1 2 3 4
10) The INTA cycle consists of
3T-states 4T-states
5T-states 6T-states
11) TRAP can be considered as
RST3.5 RST4.5
RST4 RST5
12) RIM is used to check whether
The write operation is done or not
The interrupt is masked or not
Both and
None of the above
13) Vectored location for RST3 is
0020H 0024H
0018H None of the above
14) RAM may be
Static RAM Dynamic RAM
Both and None of the above
15) Permanent data and instructions storing memory is
RAM chip ROM chip
DRAM chip None of the above
16) Choose the correct statement for I/O mapped I/O mode
Memory space available is greater
IN and OUT are the only data transfer instruction available
Memory space available is lesser
I/O mapped I/O space greater than memory mapped I/O
SLR-ER 13
17) The disadvantage of memory mapped I/O over I/O mapped I/O is
Faster
Many instructions supporting memory mapped I/O
Require a bigger address decoder
None of the above
18) What is the size of I/O ports in 8255
8 bits 16 bits 4 bits 1 bit
19) Group A signals of 8255 consists of
Port A and Port Cupper
Port A and Port B
Port B and Port Cupper
Port B and Port Clower
20) Which port is associated with mode 2 of 8255
Port A Port B
Port C None of the above
SECTION I
2. Write short note on (any four)
Pin out diagram
Data lines
Data transfer instructions
Call and Ret subroutine related instructions
I/O read and I/O writes.
3. Explain in brief internal architecture of 8085 microprocessor. 10
What are the different addressing modes of 8065 10
OR
Describe Machine cycles of Opcode Fetch and Operand Fetch. 10
SLR-ER 13
SECTION II
4. Write short note on (any four)
Hardware interrupts
Interrupt acknowledge Machine cycle
BSR feature of 8255 interface controller
RAM and ROM Memory
Synchronous and asynchronous serial communication.
5. Explain programmable interval Timer 8253 with block diagram. 10
What do you mean by I/O mapped I/O and Memory Mapped I/O 10
OR
Explain in detail vectored interrupt and non-vectored interrupt. 10