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Seat No.: Enrolment
GUJARAT TECHNOLOGICAL UNIVERSITY
ME SEMESTER IV EXAMINATION SUMMER 2019
Subject Code: 2742604 Date: 03/05/2019
Subject Name: Mutli gate transistors
Time: 02:30 PM To 05:00 PM Total Marks: 70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
Q.1

What do you understand by volume inversion in double-gate SOI MOSFET device? What are its different advantages reported in the literature? List out the different scattering phenomena which affect mobility.
07

Draw two-stage Miller compensated operational amplifier, and discuss performance comparison w. r. t. various performance parameters of op-amp for following cases:
1. Planar MOSFET based op-amp
2. MuGFET based op-amp (do comparison by taking different LG for MuGFET devices)
07
Q.2

Plot electron concentration in silicon body as a function of distance from front gate of a symmetrical Double-Gate MOS structure, and mention observations for the following cases:
1. At different Gate voltage. (assume fin thickness equal to 10 nm)
2. For different silicon film thickness (e.g. 5 nm, 10 nm, 20 nm, 30 nm) and at constant gate voltage
07

Discuss asymmetry effects such as different gate voltages and oxide thickness on the distribution of electron concentration in the silicon body of Double-Gate MOS structure.
07
OR

Discuss behavior of surface scattering phenomenon affecting mobility parameter of double-gate SOI MOSFET device.
07
Q.3

Define natural length parameter of MOSFET device and obtain expression of the same for double-gate SOI MOSFET device.
07

Explain corner effect in multigate transistor device with the help of dgm/dVG plot as well as discuss its dependence on radius of corners and channel doping concentrations.
07
OR
Q.3

Obtain threshold voltage expression for double-gate SOI MOSFET taking into account quantum mechanical effect.
07

What do you understand by inter-subband scattering? Discuss its effect on IDS VGS characteristics.
07
Q.4

Discuss fabrication of Tri-gate MOSFET on an SOI substrate with necessary diagrams.
07

Draw structure of silicon nanowire transistor and obtain expression for gate capacitance of the same.
07
OR
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Q.4

Obtain expression for natural length parameter of double-gate SOI MOSFET device assuming that punchthrough takes place at center of fin. Also obtain expression for effective Fin width taking into account impact of gate oxide equivalent to a constant offset of physical fin width.
07

Discuss fin surface crystal orientation and its effect on mobility. Draw approximate layout of 6-T SRAM cell with mixed 100) fins directions.
07
Q.5

How can we vary VT in double-gate SOI MOSFET device? Discuss performance of a device/circuit designed using double-gate SOI MOSFET device w. r. t. leakage current and speed as a function of ratio of physical channel length to fin thickness (WFIN).
07

Compare planar MOSFET and double-gate SOI MOSFET w. r. t. following device parameters:
1. Transconductance
2. Output conductance
3. Intrinsic transistor gain
07
OR
Q.5

Plot following characteristics of double-gate SOI MOSFET for three different thickness values of fins (e.g. TFIN1 TFIN2 TFIN3).
1. IDS VGS
2. IDS VDS
07

Discuss the effects of charge trapping in high-k dielectric along with equivalent circuit approach for the simulation of same.
07