Reg. No.
B.E. B.Tech. DEGREE EXAMINATION, MAY 2017
Sixth Semester
Electronics and Communication Engineering
01UEC604 VLSI DESIGN
(Regulation 2013)
Duration: Three hours Maximum: 100 Marks
Answer ALL Questions
PART A (10 x 2 20 Marks)
1. What is the objective of Layout rules?
2. List the various issues in Technology-CAD.
3. What is meant by crosstalk?
4. What is meant by design margin?
5. State the reasons for the speed advantage of CVSL family.
6. State any two criteria for low power logic design.
7. What is the need for testing?
8. What is mean by logic verification?
9. Mention the possible values which are allowed in Verilog HDL.
10. What are gate primitives?
Question Paper Code: 31464
2
31464
PART B x 16 80 Marks)
11. Explain in detail about ideal I-V characteristics and non-ideal characteristics of MOSFET.
Or
With a neat diagram discuss in detail about DC transfer characteristics of CMOS inverter.
Explain in detail about Ideal I-V characteristics of CMOS.
12. What is Power Dissipation? Explain the various ways to minimize the static and dynamic power dissipation.
Or
Discuss in detail about the resistive and capacitive delay estimation of the CMOS inverter circuit.
13. Explain the issues related to the design of low power logic design.
In short explain about static CMOS design.
Or
Explain in briefly about Synchronizers.
14. Describe in detail, the various manufacturing test principles in CMOS testing.
Or
Explain the method of boundary scan test in detail.
15. Write a Verilog HDL for an 8-bit ripple carry adder using structural model.
Or
Explain behavioral and gate level modeling with suitable example.