Supplementary Examinations, May 2018
(Regulations: VCE-R11/R11A)
VLSI DESIGN
(Electronics and Communication Engineering)
Date: 10 May, 2018 AN Time: 3 hours Max Marks: 75
Answer ONE question from each Unit
All Questions Carry Equal Marks
Unit I
1. Derive the expression for drain current of PMOS Transistor in linear region and saturation
region starting from fundamentals.
10M
Explain channel length modulation.
5M
2. With a neat circuit diagram, explain the operation of basic differential amplifier and
CMOS Inverter.
10M
With a neat sketch, explain the working of depletion mode device.
5M
Unit II
3. Briefly explain epitaxy, deposition, ion-implantation and diffusion in CMOS technology. 10M
What are the advantages of Silicon on Insulator technology?
5M
4. With a neat diagram, explain Twin-Tub CMOS process. 8M
Write short notes on Latchup Triggering.
7M
Unit III
5. With a neat diagram, explain lambda-based design rules for contact cuts. 8M
Draw the circuit diagram and stick diagram for nMOS and CMOS inverter.
7M
6. Draw the circuit schematic and stick diagram of CMOS 2-input NAND gate. 8M
With a neat diagram, explain the double metal, double poly CMOS rules.
7M
Unit IV
7. Draw the layout of 2 input NOR gate. 7M
Draw the Dynamic CMOS circuit and CMOS Complementary circuit for
8M
8. Design a dynamic 2 input NOR gate and explain its operation. 7M
With a neat circuit diagram, explain the operation of domino logic 3 input AND gate.
8M
Unit V
9. With an example briefly explain the Stuck-AT Faults models. 7M
Briefly explain Level-Sensitive Scan Design (LSSD) approach for testing.
8M
10. What are the self-test techniques? Explain any one technique in briefly. 8M
Write short notes on Observability, Controllability and Fault Coverage in manufacturing
test principles.
7M