Hall Ticket No Question Paper Code: AEC008
INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
B.Tech V Semester End Examinations (Supplementary) January, 2019
Regulation: IARE R16
INTEGRATED CIRCUITS APPLICATIONS
Time: 3 Hours (Common to ECE EEE) Max Marks: 70
Answer ONE Question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
UNIT I
1. Derive the expression for Q Point, ZI and Z0 of a dual input balanced output differential
amplifier.
Determine the output voltage of the differential amplifier having input Voltages V1=1mV and
V2=2 mV. The amplifier has a differential gain of 5000 and CMRR 1000.
2. Explain the working principle of a BJT differential amplifier with active load.
An Op amp has a slew rate of 1.5V/μs. What is the maximum frequency of an output sinusoid
of peak value 10 V at which the distortion sets in due to the slew rate limitation?
UNIT II
3. With the help of neat diagrams explain the operation of Schmitt Trigger using IC741.
In the following Figure R1 10 k
Rf 100k
vi 1V. A load of 25 k
is connected to
the output terminal. Calculate i1 v0 (iii)iL Total current i0 into the output pin.
Figure 1
4. Draw the circuit using Op-amp as instrumentation amplifier and explain its working function.

In the given circuit shown in Figure let R1 k
Rf 20 k
and vi =1V. A load resistor
of 5 k
is connected to the output terminal. Calculate
v0 ACL (iii)iL Total current i0 indicating proper direction of flow.
Page 1 of 2
Figure 2
UNIT III
5. Draw the block diagram of Phase Locked Loop(PLL) and briefly explain about each block in
PLL.
Design a wide Band Pass Filter having fl 400 Hz, fh 2 kHz and pass band gain of 4. Find
the value of Q of the filter.
6. With the help of circuit diagrams and waveform, explain the working of 555 Timer as Astable
multivibrator and derive an expression for frequency.
Design a Second order Butterworth Low pass filter having upper cut off frequency 2 KHz. Assume
necessary data.
UNIT IV
7. What output voltage would be produced by a D/A converter whose output range is 0 to 10 V
and whose input binary number is
10 for a 2-bit D/A Converter 0110 for a 4-bit D/A Converter
10111100 for an 8-bit D/A Converter
With the help of neat circuit diagram and waveform explain the operation of Dual Slope ADC.

8. Explain voltage mode and current mode operations of R-2R ladder type DAC.
A Dual slope ADC uses a 16-bit counter and a 4 MHz clock rate. The maximum input voltage
range is +10 V. The maximum integrator output voltage should be -8V when the counter has
cycled through 2n counts. The capacitor used in the integrator is 0.1μF. Find the value of the
resistor R of the integrator.
UNIT V
9. What is a carry look ahead adder? Design and implement carry look ahead adder using logical
gates.
Implement the 4-bit, 8-state Johnson counter using 74x194 and draw the corresponding timing
diagram.
10. Compare synchronous and asynchronous counters. Design 4-bit synchronous counter using Tflip-
flops.
Implement the parallel input to serial output shift register using 74x163 and 74x166.