Hall Ticket No Question Paper Code: BCS003
INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
M.Tech I Semester End Examinations (Regular) January/February, 2018
Regulation: IARE-R16
HIGH PERFORMANCE ARCHITECTURE
(Computer Science and Engineering)
Time: 3 Hours Max Marks: 70
Answer ONE Question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
UNIT I
1. How processor parallelism is achieved? Explain with a suitable example for asynchronous processor
parallelism.
Solve the dependence equation for the below code
DO I 1 N

ENDDO
2. Write advantages and disadvantages of superscalar and VLIW processor.
Construct all direction vectors for the following loop and indicate the type of dependence associated
with each.
DO K =1,100
DO J 100
DO I 100
B
ENDDO
ENDDO
ENDDO
UNIT II
3. Discuss briefly ZIV test and SIV test. Differentiate the delta test and multiple- subscript tests.

Apply the loop peeling for the following loop
DO 10
S1:
ENDDO
4. Define the following terms with suitable examples.
ZIV -subscript SIV -subscript MIV-subscript
Explain briefly the concept of constraints and constraint vectors with suitable examples.
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UNIT III
5. Differentiate Fine-Grained parallelism and Coarse-Grained parallelism.
List drawbacks of scalar expansion and also state the solutions to prevent these drawbacks.[7M]
6. Discuss loop alignment and loop replication algorithm with an example.
Indiscriminate loop fusion may reduce parallelism Justify with a suitable example.
UNIT IV
7. Identify how register allocation plays a vital role in compiler optimization and list the types of
cache blocking.
A two way set associative cache memory uses blocks of four words. The cache can accommodate
a total of 2048 words from main memory. The main memory size is 128K X 32.
Formulate all pertinent information required to construct the cache memory.
What is the size of cache memory?
8. What are the two ways to remove backward branches? Explain with solutions.
What is software perfecting? What are its advantages and disadvantages? How can the disadvantages
be minimized?
UNIT V
9. Explain the types of data dependence for register reuse.
Apply scalar replacement for the following code
DO I N
C

ENDDO
10. Explain about dependence spanning multiple iterations with example code.
Identify how data dependence is calculated if registers are reused and how can we improve register
reuse in loop carried and loop independent reuse.
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