VARDHAMAN COLLEGE OF ENGINEERING
(AUTONOMOUS)
B. Tech VI Semester Regular Examinations, May 2018
(Regulations: VCE-R15)
LOW POWER VLSI DESIGN
(Electronics and Communication Engineering)
Date: 28 May, 2018 FN
Time: 3 hours
Max Marks: 75
Answer ONE question from each Unit
All Questions Carry Equal Marks
Unit I
1.

Explain body effect and sub-threshold current in long channel MOSFET.
9M

With necessary diagram explain the MIS structure and its energy bands when it is unbiased.
6M
2.

Derive an expression for dynamic power dissipation in CMOS Circuits, taking in to account the charging and discharging of capacitance in CMOS circuits.
6M

Briefly explain the basic principles of low power VLSI design?
9M
Unit II
3.

Write the two sources of uncertainty that affects the delays of the circuit.
6M

Explain the power sensitivity technique to obtain bound average power with flowchart.
9M
4.

Describe the technique of estimating average power in sequential circuits.
8M

Express P(X2TXTX0), P(X2TX'TX0) P(X2TX0)in terms of its probabilities and normalized activities a(aX).
7M
Unit III
5.

Explain the first order difference algorithm level transforms for low power in behavioral transformation.
7M

With an example, briefly explain the power optimization using operation substitution.
8M
6.

Briefly explain the power efficient pre-computation logic using shannon's expansion.
8M

Explain the circuit activity driven architectural transformations with diagrams.
7M
Unit IV
7.

With a circuit diagram, explain the pre-charge low differential current switch logic operation.
7M

Explain the following:
i. Reverse-Bias PN junction leakage current
ii. Weak Inversion
8M
8.

With an example, explain the following logic families and discuss about power and performance of these logic families:
i. NMOS Logic
ii. DCVS Logic
8M

Explain the following logic families with examples:
i. Pass-transistor logic
ii. Domino Logic
Comment about power and performance of each logic families.
7M
Unit V
9.

With a circuit diagram explain the operation of 2 input adiabatic NAND Switch.
7M

Explain the operations of Adiabatic SRAM Core.
8M
10.

Briefly explain the operation of adiabatic dynamic logic CMOS inverter with a circuit diagram.
7M

Explain the following software power estimation:
i. Architecture level power estimation
ii. Bus switching Activity