VARDHAMAN COLLEGE OF ENGINEERING
(AUTONOMOUS)
B. Tech VI Semester Regular Examinations, May 2018
(Regulations: VCE-R15)
DIGITAL SYSTEM DESIGN
(Electronics and Communication Engineering)
Date: 24 May, 2018 FN Time: 3 hours Max Marks: 75
Answer ONE question from each Unit
All Questions Carry Equal Marks
Unit I
1. Write the five possible representations of combinational logic functions and explain. 7M
Compare static hazards with dynamic hazards by taking suitable example.
8M
2. Derive and Design the alarm circuit from the logic expressions and write its sum of
product version.
8M
Design and evaluate the distinguished 1-cell, Prime implicant and essential prime
implicant for the following:
i. F
ii. F
7M
Unit II
3. Describe the three state devices with examples. 8M
Develop the VHDL code for 4 to 1 line multiplexer using dataflow modeling.
7M
4. Discuss the timing concepts with analysis tool for combinational circuits. 7M
Compare PLA with PAL. Realize the following functions using 4×5×3 PLA.
i. F1
ii. F2
iii. F3
8M
Unit III
5. What is bistable element? Give the digital analysis and analog analysis for the same. 7M
Give the clocked synchronous state machine structure for moore machine and melay
machine.
8M
6. What are the different steps involved in designing a clocked synchronous state
machine?
8M
What is scan flipflop? Explain the master slave SR flipflop.
7M
Unit IV
7. Discuss the race free state assignments with examples. 7M
Describe the state machine synthesis using transition list.
8M
8. Define and explain the following:
i. PLD
ii. FPGA
iii. SM chart
7M
Differentiate Mealy and Moore Sequential networks. Design Mealy sequential network
for the following sequence, output is high for non zero present state when input x=0
using edge triggered JKFF. for for x=1.
8M
Cont…2

Unit V
9. Explain fault diagnosis of a combinational circuit by conventional method. 8M
Evaluate the test patterns of given circuit to detect at x4.
Fig.1
2 3 1 1 4 Z x x x x x
7M
10. Illustrate single, multiple and bridging logical fault model with by taking suitable
example.
7M
Explain the following with respect test pattern generation:
i. Random testing
ii. Transition count testing