Exam Details
| Subject | dsp processors and architectures | |
| Paper | ||
| Exam / Course | computer science and engineering | |
| Department | ||
| Organization | Vardhaman College Of Engineering | |
| Position | ||
| Exam Date | June, 2017 | |
| City, State | telangana, hyderabad |
Question Paper
Hall Ticket No:
Question Paper Code B3603
(AUTONOMOUS) M. Tech I Semester Supplementary Examinations, June 2017
(Regulations: VCE-R15) DSP PROCESSORS AND ARCHTECTURES
(Embedded Systems) Date: 09 June, 2017 AN
Time: 3 hours
Max Marks: 70
Answer any FIVE Questions
Each Question carries equal marks
1.
Distinguish between Interpolation and decimation filter with schematic diagrams.
8M
An analog signal is sampled at the rate of 8KHz, if 512 sample of this signals are used to compute DFT, Determine the analog and digital frequency spacing between adjacent elements. Also determine analog and digital frequencies corresponding to K=64.
6M
2.
Explain in detail about the Fixed Point Format and Floating Point Format.
7M
Find the decimal equivalent of the floating point binary number 1011000011100. Assume a format similar to IEEE -754 in which the MSB is the sign bit followed by 4 exponent bits followed by 8 bits for the fractional part.
7M
3.
What distinguishes a digital signal processor from a general purpose microprocessor with regard to basic capabilities?
7M
Explain the operation of 4X4 Braun multiplier with neat structure.
7M
4.
What is zero over head looping? How this feature is advantageous in DSP processor?
Explain with an example.
7M
What is pipelining? Explain how pipelining is useful for reducing the number of instruction cycles with examples.
7M
5.
Explain any two on-chip peripherals in TMS320C54XX processor.
7M
Explain circular addressing mode in TMS320C54XX processor with neat block diagram.
7M
6.
Explain with a neat diagram the implementation of FIR Filters.
7M
Represent each of the following as 16-bit numbers in desired Q-notation:
i. 0.3125 as a Q15 number
ii. 2.125 as a Q7 number
7M
7.
Explain the bit-reversed index generation.
7M
A 4-point FFT is to be implemented using DIT-FFT method on TMS320C54XX. Give the FFT implementation structure and also explain the algorithm that computes the output of each stage.
7M
8.
Explain how the parallel I/O Converter) is interfaced in DSP processors.
7M
Explain Multichannel Buffered Serial Port (McBSP) TMS320C54XX series processor.
7M
Question Paper Code B3603
(AUTONOMOUS) M. Tech I Semester Supplementary Examinations, June 2017
(Regulations: VCE-R15) DSP PROCESSORS AND ARCHTECTURES
(Embedded Systems) Date: 09 June, 2017 AN
Time: 3 hours
Max Marks: 70
Answer any FIVE Questions
Each Question carries equal marks
1.
Distinguish between Interpolation and decimation filter with schematic diagrams.
8M
An analog signal is sampled at the rate of 8KHz, if 512 sample of this signals are used to compute DFT, Determine the analog and digital frequency spacing between adjacent elements. Also determine analog and digital frequencies corresponding to K=64.
6M
2.
Explain in detail about the Fixed Point Format and Floating Point Format.
7M
Find the decimal equivalent of the floating point binary number 1011000011100. Assume a format similar to IEEE -754 in which the MSB is the sign bit followed by 4 exponent bits followed by 8 bits for the fractional part.
7M
3.
What distinguishes a digital signal processor from a general purpose microprocessor with regard to basic capabilities?
7M
Explain the operation of 4X4 Braun multiplier with neat structure.
7M
4.
What is zero over head looping? How this feature is advantageous in DSP processor?
Explain with an example.
7M
What is pipelining? Explain how pipelining is useful for reducing the number of instruction cycles with examples.
7M
5.
Explain any two on-chip peripherals in TMS320C54XX processor.
7M
Explain circular addressing mode in TMS320C54XX processor with neat block diagram.
7M
6.
Explain with a neat diagram the implementation of FIR Filters.
7M
Represent each of the following as 16-bit numbers in desired Q-notation:
i. 0.3125 as a Q15 number
ii. 2.125 as a Q7 number
7M
7.
Explain the bit-reversed index generation.
7M
A 4-point FFT is to be implemented using DIT-FFT method on TMS320C54XX. Give the FFT implementation structure and also explain the algorithm that computes the output of each stage.
7M
8.
Explain how the parallel I/O Converter) is interfaced in DSP processors.
7M
Explain Multichannel Buffered Serial Port (McBSP) TMS320C54XX series processor.
7M
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