Hall Ticket No:
Question Paper Code B3403
(AUTONOMOUS) M. Tech I Semester Supplementary Examinations, June 2017
(Regulations: VCE-R15) CMOS VLSI DESIGN
(Digital Electronics and Communication Systems) Date: 09 June, 2017 AN
Time: 3 hours
Max Marks: 70
Answer any FIVE Questions
Each Question carries equal marks
1.
Explain the concept of capacitance estimation in MOS transistors.
8M
Derive an expression for drain source resistance in V-I characteristics of MOS transistor.
6M
2.
Explain and derive the necessary DC region equations of a CMOS inverter.
9M
Explain the DC noise margin of a CMOS logic.
5M
3.
Explain the RC Model in transient modeling of nFET.
6M
Consider the circuit shown in Fig.1 below:
i. What is the logic function performed by this circuit
ii. What is VOH for this circuit
iii. What is VOL for this circuit
Assume VDD 3.3V, VT0n 0.75V, 0.58 V and γ 0.071 v1/2 for the nFET and |VT0p| 0.9 0.6 V and γ 0.135 v1/2 for the pFET.
Fig.1
8M
4.
Design a CMOS 1-bit full adder circuit.
6M
Explain mirror circuits with an example.
8M
5.
Design a two input XOR gate using transmission gate using not more than six transistors. Also explain its operation.
6M
Design a positive edge triggered D-register using transmission gates. Explain its operation with the help of timing diagram and truth table. Also write the expressions for setup time and clock to Q delay of the D-register designed in terms of the transmission gate delays and the inverter delay.
8M
6.
Explain briefly bootstrapping in Dynamic logic circuits.
6M
Design a C2MOS D-register. Explain its operation. Also explain how C2MOS D-register is insensitive to clock skew?
8M
7.
Explain pre-charge and evaluation phases in Dynamic logic families with an example.
8M
Explain Charge sharing and charge leakage problems in Dynamic logic families.
6M
8.
Explain the operation of CVSL Buffer/Inverter circuit.
8M
Explain the stable states of PFET latch.
6M