Hall Ticket No:
Question Paper Code B3601
(AUTONOMOUS) M. Tech I Semester Regular/Supplementary Examinations, December 2017
(Regulations: VCE-R15) MICROCONTROLLERS FOR EMBEDDED SYSTEM DESIGN
(Embedded Systems) Date: 27 December, 2017 FN
Time: 3 hours
Max Marks: 70
Answer any FIVE Questions
Each Question carries equal marks
1.
Illustrate the memory organization of 8051 microcontroller with the help of a neat diagram.
7M
Distinguish between Von Neumann and Harvard architecture with suitable sketches and relevant examples. Sketch a neat figure of PSW, explain its structure and fields.
7M
2.
Explain the different types of CALL instructions available in 8051 with examples.
6M
Illustrate the dual role functionality of Port 2 in 8051 microcontroller. Write the following programs
i. Create a square wave of 50% duty cycle on bit 0 of port 1
ii. Create a square wave of 66% duty cycle on bit 3 of port 1
8M
3.
List and explain the different bit handling instructions with examples.
8M
Assuming the ROM space starting at 250H contains "America", write a program to transfer the bytes into RAM locations starting at 40H.
6M
4.
Assume that register A has packed BCD. Write a program to convert packed BCD to two ASCII numbers and place them in R2 and R6.
5M
I. Write an assembly language program to transfer the value 41H serially (one bit at a time) via pin P2.1. Put two highs at the start and end of the data. Send the LSB first.
II. Define the checksum byte in ROM and its importance. Consider 4 bytes of hex data 25h, 62h, 3fh and 52h
i. Find the checksum byte
ii. Perform the checksum operation for data integrating
iii. Change the value of second 62h to 22h, and show how the checksum detect the error
9M
5.
List and compare the features of the three main design technologies. What are the benefits of using each of the three different design technologies?
7M
Design a single purpose processor that outputs Fibonacci numbers up-to places. Start with function computing the desired result, translate into state diagram and sketch a probable data-path.
7M
6.
Illustrate the operation of general purpose processor with the help of neat basic architecture and an example.
7M
What is an Instruction-set simulator? Explain the testing and debugging phase of developing programs and the various tools needed for the same.
7M
Cont…2

7.
What is PWM? Illustrate the role of PWN in embedded applications and Explain how speed control of a DC motor is achieved using a PWM with suitable example.
7M
What is UART? Illustrate how the serial transmission is carried out using a universal asynchronous receiver/transmitter (UART) highlighting the role of start bit, stop bit, baud rate and parity bit with relevant figure.
7M
8.
List and explain the various Cache mapping techniques with relevant diagrams.
7M
Given the following three cache designs, find the one with the best performance by calculating the average cost of access. Show all calculations.
i. 4 Kbyte, 8-way set associative cache with a miss rate; cache hit costs one cycle, cache miss costs 12 cycles
ii. 8 Kbyte, 4-way set-associative cache with a miss rate; cache hit costs two cycles, cache miss costs 12 cycles
iii. 16 Kbyte, 2-way set-associative cache with a miss rate; cache hit costs three cycles, cache miss costs 12 cycles
7M