Hall Ticket No:
Question Paper Code B3403
(AUTONOMOUS) M. Tech I Semester Regular Examinations, January 2018
(Regulations: VCE-R15) CMOS VLSI DESIGN
(Digital Electronics and Communication Systems) Date: 02 January, 2018 FN
Time: 3 hours
Max Marks: 70
Answer any FIVE Questions
Each Question carries equal marks
1.
Using bulk charge model explain the current voltage characteristics of the MOSFET.
9M
What is the significance of body bias? Explain how it affects threshold voltage.
5M
2.
Define the following with reference to CMOS inverter design:
i. Noise margin
ii. Maximum switching frequency
4M
How can the propagation delay be estimated in a CMOS inverter? Derive the delay for different transitions.
10M
3.
Write a brief note on MOSFET application as switch logic.
6M
With relevant figures explain how series connected MOSFETS increase voltage and power handling.
8M
4.
Construct a CMOS logic gate to implement the function
7M
Draw the schematic of a 3 bit CMOS NOR gate and explain its functioning.
7M
5.
Explain the operation of a TG based D Flipflop with relevant schematic and timing diagram.
8M
Implement XOR function using CMOS transmission gates.
6M
6.
Highlight the issue of charge leakage in dynamic design and suggest a solution to eliminate it.
7M
Explain clock feed through and its significance in dynamic design.
7M
7.
What are the principles of dynamic logic? Explain with relevance to precharge and evaluation citing suitable example.
8M
Cascade two dynamic gates and analyze its performance.
6M
8.
Discuss any one variation on CVSL logic.
6M
Design a generic differential (Cascode Voltage Switch) logic and analyze its performance.
8M