M.Sc. (Semester IV) (CBCS) Examination Nov/Dec-2018
Electronics
MIXED SIGNAL BASED SoC DESIGN
Time: 2½ hrs Max. Marks: 70
Instructions: Attempt five questions.
Q. 1 and 2 are compulsory.
Answer any three questions from Q.3 to Q.7.
Figures to the right indicate full marks.
Q.1 Choose correct answer. 08
The continuous tome analog block can be configured as
PGA Integrator
Inverting Amplifier All of these
The internal main oscillator of PSoC1 device has frequency.
32.768 KHz 732 KHz
24MHz 12 MHz
The PSoC devices are having mA current sinking capacity per
pin.
25 mA 10mA
20mA 15mA
The SRAM of PSoC1 Device is segmented into pages of 256
bytes.
2 4
6 8
In continuous time analog block of PSoC devices the gain can be
configured up to
2 256
8 48
In programmable digital blocks Auxiliary input is used for
communication.
Parallel SPI
RS232 None of these
In switched capacitor inverting amplifier, the gain is given by
CA/CF CF/CA
RF/FA CA x CF
In ΔΣ ADC the quantization error is given by
2Δ Δ
Δ/2 None of these
Page 2 of 2
SLR-VJ-275
State True or false. 06
As per the hardware configurability, the global odd numbered buses are
interfaced with global odd numbered ports only.
In PSoC the clock sub system is not configurable.
Continuous time analog block can be configured as instrumentation
amplifier.
For delta sigma ADC, for down conversion of frequency of signal,
decimator block is not required.
The clocks used to ensure the switched capacitor analog components
should be out of phase.
In case of Cypress PSoC the 8051 core is used for processing.
Q.2 Answer any two of the following. 10
With block diagram, describe the general architecture of programmable
digital block.
Write a note on interrupt subsystem
Based on SC principle, describe the design of summing amplifier.
With block diagram describe an array of programmable analog block. 04
Q.3 What do you mean by mixed signal based SoC design? Discuss the salient
features of Cypress programmable System on Chip.
08
Describe in details an architecture of system bus of PSoC1 devices. 06
Q.4 What do you mean by programmable communication blocks of PSoC
device? Describe in detail programmable UART block of PSoC device.
08
Write a note memory sub- system of PSoC devices. 06
Q.5 Describe the basic principle of Delta Sigma ADC. With suitable diagram
describe an architecture of Delta Sigma ADC of PSoC device.
08
Describe internal architecture of programmable analog blocks. Discuss
types of configurable analog inputs.
06
Q.6 With the suitable block diagram describe an array of programmable digital
blocks. Discuss fundamental architecture of programmable digital block.
08
With suitable block diagram describe the design of mixed signal based
system on chip for measurement of relative humidity.
06
Q.7 What are subsystems of PSoC1 device? Describe in detail Clock system of
the PSoC devices.
08
Write a note on programmable gain amplifier. 06