M.Sc. (Semester III) Examination Nov/Dec-2018
Electronics
CMOS ANALOG CIRCUIT DESIGN
Time: 2½ Hours Max. Marks: 70
Instructions: All questions are compulsory.
Use of Log table and calculator is allowed.
Draw neat and labeled diagram wherever necessary.
Figures to the right indicate full marks.
Q.1 Choose correct answer 14
The substrate of the nMOS device, when biased in active mode, is always at
potential.
Strong negative Strong positive
Weak positive Floating
The differential amplifier stage of CMOS operational amplifier is referred as
Voltage amplifier Transconductance amplifier
Push-pull amplifier None of these
If gate of two nMOS transistors are coupled together and biased for same
potential, then the circuit is called
active load passive load
current mirror voltage amplifier
If gates of the two MOS transistors are applied to the same potential and
drains are also connected to one and same power supply, then current
through one device is 4.35 mA. What is current through another MOS
device?
4.35 mA 9.15 mA
17 mA 43.5 mA
In switched capacitor circuit the resistor is given by
R 1/FC R TC
R F/C R FC
In MOS technology the sheet resistance is measured in unit of


To remove a portion of SiO2 layer is used as etching material.
HF HCI
H3PO4 All of these
The Source follower configuration of MOS device is used as
High gain stage Output stage
Input stage All of these
For MOS transistor the transconductance, is given by
β μCox β W/L
β W. L β μCox W/L
10) In classical two stage CMOS Operational amplifier, the impedance of output
stage
is very high depends upon nature of load
is low all of these
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11) The n-well means the region in which doping concentration
of n-type impurity is very low of p-type impurity is very low
of n-type impurity is very high of p-type impurity is very high
12) In switched capacitor, the clocks and should be
Non-overlapping and in phase
Overlapping and in phase
Non-overlapping and Out of phase
Overlapping and Out of phase
13) The drain to source saturation potential is expressed as
VDS(sat) VGS VDD VDS(sat) VGS VT
VDS(sat) VGS VDS(sat) VDD/2
14) In case of the switched capacitor inverting amplifier, the gain is given by
A
Ci x CF CF Ci
Ci CF CF
2
Q.2 Attempt any four of the following 08
What do you mean by Bi-CMOS transistor?
What is threshold potential?
Draw circuit diagram for current mirror load differential amplifier.
Why first stage of MOS operational amplifier is called as
transconductance amplifier?
Draw circuit diagram for switched capacitor based integrator circuit.
Answer any two of the following 06
Describe in detail, the use of MOS device as a diode.
Write a note on MOS devices as a current source and sink.
What do you mean by channel width modulation?
Q.3 Answer any two of the following 08
Write a note on output amplifier.
Discuss Band Gap as reference source.
Write a note on current mirror circuit.
Answer any one of the following 06
What do mean by passive components in MOS technology? Describe
parasitic capacitance.
Write a note on switched capacitor summing amplifier.
Q.4 Answer any two of the following 10
Using nMOS transistor, discuss the design of differential amplifier.
Describe in detail, the current sink and current source circuits.
What do you mean by CS amplifier? Discuss the inverter circuits with
different kinds of loads.
Answer any one of the following 04
Discuss the term nMOS Transistor as a diode.
Describe Large signal model of CS MOS amplifier.
Q.5 Describe any two of the following 14
With suitable diagram explain current mechanism in nMOS device. Derive
expression for drain current.
Describe in detail the design of two stage classical and cascoded
operational amplifier.
What do you mean by emulation of switched capacitor circuit as register?
Using SC, describe the design of inverting and non-inverting amplifier.