F.Y. M.Tech. (Electronics) (Semester (CBCS) Examination, 2018
Elective I Analog and digital CMOS VLSI design
Day and Date Wednesday, 12-12-2018day, 0-0-2018 Max.Marks 70
Time 10.00 a.m. to 1.00 p.m. 0.00 a.m.
Instructions Q. 1 and Q. 5 are compulsory.
Solve any two questions from Q. 2 to Q. 4 for Section I.
Solve any two questions from Q. 6 to Q. 8 for Section II.
Figures to the right indicate full marks.
Section I
1. What is dynamic behavior of CMOS inverter 5
E xplain stick diagram and layout for digital CMOS design. 6
2. C omment on speed and power dissipation in dynamic logic. 6
What is ESD protection for digital CMOS design and how it is provided 6
3. E xplain master-slave negative edge triggered register using multiplexers. 6
Explain static SR flip-flops. 6
4. Write notes on any two of the following
Metal gate technology
Ratioed logic
Wire delay models.
P.T.O.
Seat
No. Set P
Set P
SLR-MT 22 *SLRMT22*
Section II
5. E xplain small signal analysis of CS stage with diode connected load. 6
What is differential pair with MOS loads Explain in detail. 5
6. Draw circuit for differential pair with active current mirror and explain. 6
Draw circuit for common gate stage and explain its frequency response. 6
7. E xplain common mode feedback using source followers. 6
What is frequency compensation of OPAMP What are its techniques
E xplain any one of them. 6
8. Write notes on any two of the following
C S stage with diode connected load
C ascode stage
Slew rate of OPAMP.