M.Sc. DEGREE EXAMINATION APRIL/MAY 2018.
Second Semester
Electronics and Communications
DIGITAL DESIGN USING VHDL
(New CBCS Syllabus w.e.f. 2017 18)
2 1721321
Time 3 Hours Max. Marks 70
PART — A
(Short answer type questions)
Answer any FIVE of the following.
All questions carry equal marks. 6 30 Marks)
1. Explain design methodology based in VHDL.
2. Explain in detail different data types of VHDL.
3. Explain about Gajski Y-Chart in detail.
4. Define operator and explain different types of VHDL operators.
5. Write VHDL code for ful-adder.
6. Write the uses of ASIC and FPGA in digital design.
7. Explain about CPU caches.
8. List out the capabilities of VHDL.
PART — B
(Essay type)
Answer ALL questions of following.
All questions carry equal marks. 10 40 Marks)
9. Define attribute and explain different types of attributes with examples.
Or
Explain code structure of VHDL with example.

10. Write VHDL program for 4:1 MUX using CASE and IF statement
Or
Explain data flow of modelling with an example.
11. Write VHDL code for 2:4 decoder using behavioural model.
Or
Write VHDL code for J-K flip-flop.
12. What is test bench and explain types of test bench used in RTL simulation.
Or
Explain about assertion statement and wait statement with one example
each.
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