Exam Details
Subject | Logic Design | |
Paper | ||
Exam / Course | B.Tech In Computer Science And Engineering (BTCSVI) | |
Department | School of Engineering & Technology (SOET) | |
Organization | indira gandhi national open university | |
Position | ||
Exam Date | June, 2015 | |
City, State | new delhi, |
Question Paper
Implement the given Boolean function using NAND gates only:
7).
Express the complement of 11, 15) in sum of minterms form.
Draw the diagram of digital circuit for the function
c C).
Simplify the following Boolean function using QM method:
10, 11, 13, 15).
3. Implement 3-bit odd parity generator using JK flip-flop, with the help of state diagram, state table, transition table and excitation table.
Add 5 and and subtract 48 and -23 using complement method.
Implement Full adder using two half adders.
Define latch and flip-flop. Implement the D flip-flop using JK flip-flop.
What is race around condition? How can it be removed?
Explain 4-bit parallel in serial out shift register with the help of a suitable diagram.
Define modulus of counter. How can you change modulus of counter?
List the specifications of AID converter and explain dual-slope AID converter using suitable diagram.
Explain 3-bit R-2R ladder D/A converter.
8. Draw the state diagram, state table and ASM chart for a sequence detector to detect the sequence 0110.
Which TTL series is most suitable at high frequencies and which gates are suitable for the wired AND operation? Justify your answer.
Compare CMOS with TTL.
10. Write short notes on any two of the following:
2 Input CMOS NOR GATE
Decade Counter
TTL to CMOS Interface
7).
Express the complement of 11, 15) in sum of minterms form.
Draw the diagram of digital circuit for the function
c C).
Simplify the following Boolean function using QM method:
10, 11, 13, 15).
3. Implement 3-bit odd parity generator using JK flip-flop, with the help of state diagram, state table, transition table and excitation table.
Add 5 and and subtract 48 and -23 using complement method.
Implement Full adder using two half adders.
Define latch and flip-flop. Implement the D flip-flop using JK flip-flop.
What is race around condition? How can it be removed?
Explain 4-bit parallel in serial out shift register with the help of a suitable diagram.
Define modulus of counter. How can you change modulus of counter?
List the specifications of AID converter and explain dual-slope AID converter using suitable diagram.
Explain 3-bit R-2R ladder D/A converter.
8. Draw the state diagram, state table and ASM chart for a sequence detector to detect the sequence 0110.
Which TTL series is most suitable at high frequencies and which gates are suitable for the wired AND operation? Justify your answer.
Compare CMOS with TTL.
10. Write short notes on any two of the following:
2 Input CMOS NOR GATE
Decade Counter
TTL to CMOS Interface
Other Question Papers
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- Centre for Corporate Education, Training & Consultancy (CCETC)
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Subjects
- Advanced Computer Architecture
- Artificial Intelligence
- Computer Architecture
- Computer Networks
- Computer Organisations
- Cryptography And Network Security
- Data Structure
- Data Warehousing And Mining
- Database Management System
- Design and Analysis of Algorithm
- Digital Image Processing
- Discrete Maths Structure
- E-Business
- Formal Language And Automata
- Logic Design
- Microprocessor
- Mobile Computing
- Object Oriented Programming
- Operating Systems
- Parallel Algorithms
- Pattern Recognition
- Principles of Programming Lang.
- Real Time Systems
- Software Engineering
- Software Quality Engineering
- Software Reusability
- System Programming And Compiler Design
- Theory Of Computation
- Unix Internals And Shell Programming
- Web Technology