Indian Institute of Technology Guwahati

Guwahati-781039, Assam

Applications are invited for a walk in test and interview for a post of Junior Research Fellow in a DST-SERB sponsored project entitled, Performance and energy optimization in many core processors using dynamic cooperation cache memory, NoC and DRAM controller at the Department of Computer Science and Engineering, IIT Guwahati.

The appointment will be made initially for a period of 6 months which is extendable upto 1 year based on the performance or co-terminus with the project whichever is earlier. To know more about the project refer: http://www.iitg.ac.in/johnjose/MARS/projects.html

Qualification and Experience: B.E. / B.Tech in CSE/ ECE with a valid GATE score in the respective stream or M.Tech / M.E. in any CSE/ECE specialization. Candidate should be proficient in C/C++/ Verilog programming and should have a sound knowledge in computer organization & architecture and computer networks.

Scale of Pay: 25,000/-p.m (+) HRA and medical allowance as per institute norms

How to apply & Selection process: Interested eligible candidates are requested to send their applications in the prescribed format attached herewith along with a brief CV to the principal investigator via email on or before 28.07.2017. They are also requested to appear for a test and interview with their CV, filled up application form and original certificates (showing educational qualification and experience) at Seminar room, CSE department, IITG on 04.08.2017 (Friday) at 9.00 am. The test will be for one hour covering the fundamentals of digital logic, computer architecture and computer networks followed by a personal interview for shortlisted candidates.

For any clarification, Contact: John Jose (Principal Investigator)

E-mail: johnjose@iitg.ernet.in

Phone: 9048665842 / 9476950747

No TA/DA will be paid to the candidates for appearing in the test and interview.

Ref.:xCSESPNSERB01125xxJJ002

Dy. Registrar R&D