Exam Details
| Subject | digital electronics | |
| Paper | ||
| Exam / Course | b.e.(electronics and instrumentation engineering) | |
| Department | ||
| Organization | SETHU INSTITUTE OF TECHNOLOGY | |
| Position | ||
| Exam Date | May, 2017 | |
| City, State | tamil nadu, pulloor |
Question Paper
Reg. No.
B.E. B.Tech. DEGREE EXAMINATION, MAY 2017
Third Semester
Electronics and Instrumentation Engineering
01UEI306 DIGITAL ELECTRONICS
(Regulation 2013)
Duration: Three hours Maximum: 100 Marks
Answer ALL Questions
PART A (10 x 2 20 Marks)
1. What is 8421 code?
2. State De-Morgan's theorem.
3. Draw the schematic of three input TTL NAND gate.
4. Implement AND gate using NOR gate and OR gate using NAND gate.
5. Write the excitation table of JK Flip-flop.
6. Differentiate between edge triggering and level triggering.
7. Define static-0 and static-1 hazards.
8. What is race conditions?
9. Discriminate between PLA and PAL.
10. Compare EPROM with EEPROM.
PART B x 16 80 Marks)
11. Compute the minimized Boolean expression using K-map F
Or
Question Paper Code: 31536
2
31536
Given Y 10, 14, draw the K-map and obtain the simplified expression and realize using basic gates
12. Design a full adder circuit and implement with the decoder circuit. Or Design a BCD to Excess-3 converter using truth table and k-map simplification.
13. Design a mod-7 synchronous binary counter using JK flip-flops. Or Design a 3-bit synchronous counter which counts in the sequence 000, 001, 011, 010,100, 110, (repeat) 000 using D flip flop.
14. Give hazard free realization for the following Boolean function. 10, 12). Or Illustrate the concept of race free state assignment with suitable examples.
15. Realize the following function using PLA F 12, 15) d 9). Implement Binary to Gray code converter using PROM devices. Or
Discuss about static and dynamic RAM cell.
B.E. B.Tech. DEGREE EXAMINATION, MAY 2017
Third Semester
Electronics and Instrumentation Engineering
01UEI306 DIGITAL ELECTRONICS
(Regulation 2013)
Duration: Three hours Maximum: 100 Marks
Answer ALL Questions
PART A (10 x 2 20 Marks)
1. What is 8421 code?
2. State De-Morgan's theorem.
3. Draw the schematic of three input TTL NAND gate.
4. Implement AND gate using NOR gate and OR gate using NAND gate.
5. Write the excitation table of JK Flip-flop.
6. Differentiate between edge triggering and level triggering.
7. Define static-0 and static-1 hazards.
8. What is race conditions?
9. Discriminate between PLA and PAL.
10. Compare EPROM with EEPROM.
PART B x 16 80 Marks)
11. Compute the minimized Boolean expression using K-map F
Or
Question Paper Code: 31536
2
31536
Given Y 10, 14, draw the K-map and obtain the simplified expression and realize using basic gates
12. Design a full adder circuit and implement with the decoder circuit. Or Design a BCD to Excess-3 converter using truth table and k-map simplification.
13. Design a mod-7 synchronous binary counter using JK flip-flops. Or Design a 3-bit synchronous counter which counts in the sequence 000, 001, 011, 010,100, 110, (repeat) 000 using D flip flop.
14. Give hazard free realization for the following Boolean function. 10, 12). Or Illustrate the concept of race free state assignment with suitable examples.
15. Realize the following function using PLA F 12, 15) d 9). Implement Binary to Gray code converter using PROM devices. Or
Discuss about static and dynamic RAM cell.
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- application of instrumentation in aerospace and navigation
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- communication engineering
- computer architecture and organization
- control engineering
- data communication and networks
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- digital image processing
- digital signal processing
- electrical circuits and networks
- electrical machines
- electrical measurements
- electromagnetic fields
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- embedded and real time systems
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- industrial instrumentation – ii
- industrial instrumentation-i
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