M.Sc. Electronics (Semester-IV) New (CBCS) Examination, 2017
MIXED SIGNAL BASED SOC DESIGN
Day Date: Wednesday, 26-04-2017 Max. Marks: 70
Time: 02.30 PM to 05.00 PM
Instructions Answer five questions
Question 1 and 2 are compulsory
Attempt any Three from Q.3 to Q.7
Figures to the right indicate full marks.
Q.1 A Choose correct alternative 08
VC1 is derived from …..
VC2 PLL E
VC3 Sysclk
The Internal main oscillator of PSoC1 device has ……
frequency.
32.768 KHz 732KHz T
48MHz 24MHz
In ADC the ……. Criteria is used for sampling of the
analog signal.
Simpson Nerst E
Nyquist None of these
The global IO ports can be configured in ……. Modes.
2 4 6 8
In continuous time analog block of PSoC devices the gain
can be configured up to…..
2 256 48 18
In case of switched capacitor programmable analog blocks
the clocks should be…….
90o Out of phase with same frequency
In phase with different frequency
Out of phase with same frequency
All of these
In switched capacitor inverting amplifier, the gain is given by
A ……..
Page 2 of 2
CA/CF CF/CA RF/FA CA x CF
If programmable digital block is configured timer, then the
register DR0 decides for ………..
Pulse width Frequency E
Pulse period Terminal Count
State True of False 06
The delta sigma ADC is not suitable for digitization of analog
signal of high frequency.
In programmable digital block external is synchronized with
internal clock.
Continuous time analog block cannot be configured as
instrumentation amplifier.
For delta sigma ADC the decimator block is not required.
Type C SC bock has only one analog input.
In case of Cypress PSoC the 8051 core is used for
processing.
Q2 Attempt any Two 10
With block diagram, describe the general architecture of M8C
Write a note on configuration of digital block as a timer.
Write a note on system clock.
With block diagram describe an array of programmable analog
block
04
Q3 What is Nyquist theorem for sampling? Describe with suitable
block diagram general architecture of ADC
14
Describe in details an architecture of system bus of PSoC1
devices
06
Q4 With the suitable block diagram describe an array of
programmable digital blocks. Discuss fundamental architecture
of programmable digital block
08
Write a note on memory subsystem 06
Q5 What do you mean by mixed signal based SoC design? 08
Discuss the salient features of Cypress programmable System
on Chip.
With suitable block diagram describe the design of mixed signal
based system on chip for measurement of relative humidity
06
Q6 With suitable diagram describe architecture of continuous time
analog block
08
Describe use of continuous time analog block as a
instrumentation amplifier.
06
Q7 What is principle of Switched Capacitor? Describe is detail the
architecture of Type C SC block.
Write a note on interrupt subsystem.