M.Sc. (Electronics) (Semester III) (CBCS) Examination, 2017
ADVANCED DIGITAL SYSTEMS DESIGN WITH VHDL
Day Date: Thursday, 20-04-2017 Max. Marks: 70
Time: 02.30 PM to 05.00 PM
Instructions: Attempt five questions.
Question 1 and 2 are compulsory.
Attempt any Three from Q.3 to Q.7.
Figures to the right indicate full marks.
Q.1 Choose the correct answer: 08
The VHDL is utilized for design.
Analog Digital Both a b None of these
The meaning of is in Data Types STD_LOGIC_
1164.
Low 0 Weak 0 All of these
The place and route is included in endlevel design.
Back Front Both a b Mixed
The exit and next statements are used only loop
statement.
Outside Inside Both a b None of these
The package std_logic_1164 is accessed by clause.
Library Use Type Both a b
The Generate statement is statement.
Sequential Concurrent Process All of these
The value is assigned by assignment used
operator.
Signal Variable Constant All of these
The are the programming technologies used for PLD.
SRAM EPROM Flash All of these
State Truth or False: 06
The data attributes return data information regarding a data
vector.
The operator is addition operator used in VHDL code.
The wait statement is a concurrent statement.
The PLD devices are utilized for analog logic circuit design.
The operator NAND and NOR are not associative.
Page 2 of 2
The process statement is itself concurrent statement.
Q.2 Attempt two (Short Questions): 10
Explain basic terminology of VHDL.
Discuss advantages of VHDL.
Explain the syntax of process statement.
Explain the architecture of FPGA. 04
Q.3 Explain the various language element of VHDL and Explain
operator in detail.
09
Write VHDL code for 8:1 demux using behavioral modeling. 05
Q.4 State and explain the role of various types of architecture bodies
in VHDL using suitable example.
09
Write VHDL code for serial out shift register. 05
Q.5 What do you mean Attributes and Generic? Explain it with
suitable example.
09
Write VHDL code for 8-bit input comparator. 05
Q.6 Explain the LOOP statement in detail with suitable example. 09
Write VHDL code for 3:8 decoder. 05
Q.7 Explain the EDA tools. Write a note on Macrocell. 09
Write VHDL code for one digit counter. 05