Exam Details
Subject | advanced digital design with vhdl | |
Paper | ||
Exam / Course | m.sc. electronics | |
Department | ||
Organization | solapur university | |
Position | ||
Exam Date | April, 2017 | |
City, State | maharashtra, solapur |
Question Paper
M. Sc- Electronics (Semester III) (CGPA) Examination, 2017
ADVANCED DIGITAL SYSTEMS DESIGN WITH VHDL
Day Date: Thursday, 20-04-2017 Max. Marks: 70
Time: 02.30 PM to 05.00 PM
Instructions: Answer five questions.
Q. 1 and Q.2 are compulsory.
Attempt any Three from Q.3 to Q.7.
Q.1 Choose the correct alternative: 08
What is the symbol used for signal assignment?
None of these
The statements defined within process unit executes.
Sequentially Concurrently
Both a and b None of these
The VHDL editor is.
A graphic editor A C program editor
A text editor An I/O editor
How many states will there be in a 4-bit ring counter?
4 8 16 32
How many flip-flops are required to make a MOD-27 binary
counter?
3 4 5 32
On J-K flip-flop, when is the flip-flop in a race condition?
K=4 K=1 K=0 K=1
Which VHDL data type has a value of or
Signal bit Std_ logic Integer
The following VHDL ENTITY declaration code is incorrect
because:
ENTITY booly 2 IS
PORT IN bit X;OUT bit
Missing semicolon Missing "PORT END"
Mismatch in ENTITY name Incorrect ENTITY name
Page 2 of 2
State Truth of False: 06
In a priority encoder, the input with the highest priority is
represented on the output.
The gated S-R flip-flop is synchronous.
Vectors are a useful way to group like signals together.
CPLDs can be used only to implement exclusive-OR and
exclusive-NOR gates.
In a Gray code, two consecutive number differ by 1 bit.
PLDs can meet all the possible requirements of complex
digital circuitry.
Q.2 Write a note on attributes. 05
Draw and explain VHDL design flow. 05
Draw and Explain block diagram of PAL. 04
Q.3 Write VHDL code for 4-bit up down counter. 08
Write VHDL code for JK flip flop. 06
Q.4 Write VHDL code for 4-bit binary adder using 1-bit adder as a
component.
08
Explain serial input serial output right shift register. 06
Q.5 Implement the function using PLA.
ƒ 1 Σ Σ
08
Design 1-bit magnitude comparator. 06
Q.6 Design 4 bit binary to gray cod convertor. 08
Explain behavioral modeling 06
Q.7 Write a VHDL code for 4:16 decoder. 08
Write VHDL code for 4:1 multiplexer. 06
ADVANCED DIGITAL SYSTEMS DESIGN WITH VHDL
Day Date: Thursday, 20-04-2017 Max. Marks: 70
Time: 02.30 PM to 05.00 PM
Instructions: Answer five questions.
Q. 1 and Q.2 are compulsory.
Attempt any Three from Q.3 to Q.7.
Q.1 Choose the correct alternative: 08
What is the symbol used for signal assignment?
None of these
The statements defined within process unit executes.
Sequentially Concurrently
Both a and b None of these
The VHDL editor is.
A graphic editor A C program editor
A text editor An I/O editor
How many states will there be in a 4-bit ring counter?
4 8 16 32
How many flip-flops are required to make a MOD-27 binary
counter?
3 4 5 32
On J-K flip-flop, when is the flip-flop in a race condition?
K=4 K=1 K=0 K=1
Which VHDL data type has a value of or
Signal bit Std_ logic Integer
The following VHDL ENTITY declaration code is incorrect
because:
ENTITY booly 2 IS
PORT IN bit X;OUT bit
Missing semicolon Missing "PORT END"
Mismatch in ENTITY name Incorrect ENTITY name
Page 2 of 2
State Truth of False: 06
In a priority encoder, the input with the highest priority is
represented on the output.
The gated S-R flip-flop is synchronous.
Vectors are a useful way to group like signals together.
CPLDs can be used only to implement exclusive-OR and
exclusive-NOR gates.
In a Gray code, two consecutive number differ by 1 bit.
PLDs can meet all the possible requirements of complex
digital circuitry.
Q.2 Write a note on attributes. 05
Draw and explain VHDL design flow. 05
Draw and Explain block diagram of PAL. 04
Q.3 Write VHDL code for 4-bit up down counter. 08
Write VHDL code for JK flip flop. 06
Q.4 Write VHDL code for 4-bit binary adder using 1-bit adder as a
component.
08
Explain serial input serial output right shift register. 06
Q.5 Implement the function using PLA.
ƒ 1 Σ Σ
08
Design 1-bit magnitude comparator. 06
Q.6 Design 4 bit binary to gray cod convertor. 08
Explain behavioral modeling 06
Q.7 Write a VHDL code for 4:16 decoder. 08
Write VHDL code for 4:1 multiplexer. 06
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