M.Sc. (Semester IV) (CBCS) Examination Mar/Apr-2018
Electronics
MIXED SIGNAL BASED SOC DESIGN
Time: 2½ Hours
Max. Marks: 70
Instructions: Q. and are compulsory. Answer any three questions from Q.3 to Q.7 Answer any 5 questions. Figures to the right indicate full marks.
Q.1
Choose the alternatives given below.
08
The PSoC1 device from Cypress comprises an array of programmable analog blocks.
12
16
24
4
The Internal main oscillator of PSoC1 device has frequency.
32.768 KHz
732 KHz
24 MHz
12 MHz
In ADC the quantization error is given by
2Δ
Δ
Δ/2
None of these
The global IO ports can be configured in modes.
2
4
6
8
In continuous time analog block of PSoC devices the gain can be configured up to
2
256
8
48
In case of switched capacitor programmable analog blocks the clocks should be
Out of phase with same frequency
In phase with different frequency
In phase with same frequency
All of these
In switched capacitor inverting amplifier, the gain is given by A
CA/CF
CF/CA
RF/FA
CA x CF
The PSoC devices are having mA current sinking capacity per pin.
25mA
10mA
20mA
15mA
Page 2 of 2
SLR-UJ-349
State True or False.
06
As per the hardware configurability, the global odd numbered buses are interfaced with global odd numbered ports only.
In PSoC each memory page of flash is of 1K bytes.
Continuous time analog block cannot be configured as instrumentation amplifier.
For delta sigma ADC the decimator block is essential.
The clocks used to ensure the switched capacitor analog components should be in phase.
In case of Cypress PSoC the 8051 core is used for processing.
Q.2
Attempt any two of the following.
10
With block diagram, describe the general architecture of PSoC devices.
Write a note on global IO ports and their configuration.
Based on SC principle, describe the design of difference amplifier.
With block diagram, describe an array of programmable analog block.
04
Q.3
Describe the basic principal of Delta Sigma ADC.
With suitable diagram describe an architecture of Delta Sigma ADC of PSoC device.
08
Describe in details an architecture of system bus of PSoC1 devices.
06
Q.4
With the suitable block diagram describe an array of programmable digital blocks. Discuss fundamental architecture of programmable digital block.
08
Describe in detail programmable UART block of PSoC device.
06
Q.5
What do you mean by mixed signal based SoC design?
Discuss the salient features of Cypress programmable system on Chip.
08
With suitable diagram, describe in detail configuration of digital block as a timer.
06
Q.6
What is Nyquist theorem for sampling? Describe with suitable block diagram general architecture of ADC.
08
With suitable block diagram, describe the design of mixed signal based system on chip for measurement of relative humidity.
06
Q.7
What are subsystems of PSoC1 device? Describe in detail Clock system of the PSoC devices.
08
Write a note on interrupt subsystem.
06