M.Sc. (Semester III) (CBCS) Examination Oct/Nov-2017
Electronics
Advanced Digital Systems Design with VHDL
Day Date: Saturday, 18-11-2017 Max. Marks: 70
Time: 02.30 PM to 05.00 PM
Instructions: Attempt five questions.
Q. and are compulsory.
Answer any three questions from Q.3 to Q.7.
Figures to the right indicates full marks.
Q.1 Choose the alternatives given below. 08
The VHDL supports design methodology.
Top-down Bottom-up
Mixed All of these
The meaning of is in Data Types STD_LOGIC_1164.
High 1
Forcing 1 All of these
The design process is included in front end design.
Design entry Gate level netlist
Both a b None of these
The NAND and NOR operators are not
Distributive Associative
Cumulative None of these
The component declaration declares the of the component.
Name Interface
Both a b None of these
The mode of ports in entity declaration are types.
2 3
4 None of these
The value is assigned by assignment operator.
Variable Signal Q
Constant All of these
The FPGA architecture are based on to generate logic functions.
LUT Multiplexer
Macrocell Bothe a b
State True of False. 06
Simulation is a logical way of emulating the behavior of a circuit.
In architecture for an entity, all statements are concurrent.
The place and route tool belongs to back end design process.
The process statement is itself a concurrent statement.
The wait statement provides an alternate way to suspend the execution of a
process.
The component declaration is appeared in the declaration part of entity.
SLR-MJ-367
Q.2 Attempt any two. (Short questions) 10
Explain the entity using decoder.
Discuss capabilities and features of VHDL.
Discuss EDA tools for PLD design flow.
Explain the SPLD. 04
Q.3 State and explain the different types of architecture bodies for full adder. 09
Write the VHDL code for 4 bit shift register. 05
Q.4 Explain the process statement with the syntax. Explain any three
statements.
09
Write VHDL code for ALU using concurrent code. 05
Q.5 What do you mean by basic language element? Explain identifier and Data
objects in detail.
09
Write VHDL code for 8:1 Demultiplexer. 05
Q.6 Explain in detail classification PLD devices. Explain the architecture of
FPGA.
09
Write VHDL code for 4 bit binary to gray code. 05
Q.7 Explain the packages and libraries for VHDL. 09
Write VHDL code for decade counter. 05