M.Sc. (Semester III) (CBCS) Examination Oct/Nov-2017
Electronics
ADVANCED DIGITAL DESIGN WITH VHDL
Day Date: Saturday, 18-11-2017 Max. Marks: 70
Time: 02.30 PM to 05.00 PM
Instructions: Attempt five questins.
Q. and are compulsory.
Answer any three questions from Q.3 to Q.7.
Figures to the right indicates full marks.
Q.1 Choose the alternatives given below. 08
The are the programming technologies used for PLD.
SRAM EPROM
Flash All of these
The FPGA architecture are based on to generate logic
functions.
LUT Multiplexer
Macrocell Both a b
The VHDL supports design methodology.
Top down Bottom up
Mixed All of these
The Generate statement is statement.
Sequential Concurrent
Process All of these
The adding operator used in VHDL.

All of these
The meaning of is in Data types STD_LOGIC_1164.
High 1
Weak 1 All of these
The GENERIC statement is declared in of the VHDL code.
Architecture Entity Q
Process All of these
The mode of ports in entity declaration are types.
2 3
4 None of these4
State True of False. 06
The wait statement provides an alternate way to suspend the execution of a
process.
The place and route tool belongs to front end design process.
The component declaration is appeared in the declaration part of
architecture.
The LOOP statement is used to iterate through the set of concurrent
statement.
SLR-MJ-361
The generic and constant values are assigned by assignment operator.
The process statement is itself a concurrent statement.
Q.2 Attempt any two. (Short questions) 10
State in brief features of VHDL.
Explain the CPLD.
Write a note on Macrocell.
Explain the entity using controlled inverter. 04
Q.3 Discuss the basic language element of VHDL? Explain identifier and
operators in detail.
Write the VHDL code for 8 to 1 multiplexer. 05
Q.4 Explain the various types of architecture bodies for VHDL with suitable
example.
09
Write VHDL code for decade counter. 05
Q.5 Explain the PLD design flow for IC fabrication. Example the EDA tools for
PLD.
09
Write VHDL code for 8 to 3 encoder. 05
Q.6 Give the detail classification of PLD devices. Explain the FPGA in detail. 09
Write VHDL code for 4 bit gray to binary code. 05
Q.7 Explain the Attributes and Generic for VHDL. 09
Write VHDL code for ALU using concurrent statement. 05