M.Sc. (Semester III) (CBCS) Examination Nov/Dec-2018
Electronics
ADVANCED DIGITAL DESIGN WITH VHDL
Time: 2½ Hours Max. Marks: 70
Instructions: All questions are compulsory.
Answer five questions
Figures to the right indicate full marks.
Q.1 Choose the correct answer: 14
The are the programming technologies used for PLD.
SRAM EPROM
Flash All of these
The CPLD is based on architecture.
sum-of-product product-of-sum
both a b logic block
The VHDL supports methodology.
top-down bottom-up
mixed all of these
The operator NAND and NOR are not
cumulative associative
distributive all of these
The adding operator used in VHDL.

All of these
The meaning of is in Data Types STD_LOGIC_1164.
low 0
forcing 0 all of these
The GENERIC statement is declared in the VHDL code.
architecture entity
process all of these
The mode of ports in entity declaration are types.
2 3
4 5
The statement provides an alternate way to suspend the execution
of a process.
wait loop
generate halt
10) The is one of the way of design entry in the CAD process.
HDL VHDL
Verilog All of these
11) The generic and constant values are assigned by assignment
operator.


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12) The PLD devices are utilized for circuit design.
analog digital
combinational digital+analog
13) The back end design is used to create source of design.
technology physical
logic circuit
14) The VHDL is description language.
software hardware
both a b logic
Q.2 Attempt any four of the following questions. 08
Explain the features of VHDL.
What is attributes in VHDL?
State the basic language element of VHDL.
State the advantages of PLD devices.
Give the syntax of the Entity in VHDL.
Write a notes on (Any Two) 06
Explain the concept of Library in VHDL.
Explain any one concurrent statement with suitable example.
Write a note on EDA tools.
Q.3 Answer any two of the following questions. 08
Write VHDL code for Decoder using behavioral modeling.
Write VHDL code for MUX using structural modeling.
Write VHDL code for Full Adder using mixed modeling.
Answer any one of the following questions. 06
Explain the component declaration and instantiation using suitable
example.
Explain the SPLD.
Q.4 Answer any two of the following questions. 10
Write VHDL code for 7-Segment display counter.
Write VHDL code for 8-bit invertors.
Write VHDL code for parallel in serial out shift register.
Answer any one of the following questions 04
Explain the macrocell.
Describe the operator in the VHDL.
Q.5 Answer any two of the following questions. 14
Classify the PLD devices. Explain the architecture of FPGA.
Design the VHDL code for PLA.
Explain the IF statement in detail with suitable example.